High-k Gate Stack: Improved Reliability Through Process Clustering

High-k (HK) gate dielectric stack process integration is one of the most critical and challenging steps in the fabrication of CMOS. Sub-32nm targets are reached by integrating the high-k with a scaled interface layer (iL), post HK nitridation and anneal. The quality of the HK bulk material and it's interface with the iL plays a critical role in the transistor's reliability degradation. This paper investigates the reliability benefits of clustering the different HK stack process chambers on a single tool without a vacuum break. It was found that full clustering of the iL + HK + nitridation steps provides the most scalable and reliable gate stack.