High-performance Parallel Addition Using Hybrid Wave-Pipelining

Levy, J.,Nyathi, Jabulani,Delgado-Frias, J.G.

Covington, KY（2005）

Sch. of Electr. Eng. & Comput. Sci.

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摘要

Pipelining digital systems has been shown to provide significant performance gains over non-pipelined systems and remains a standard in microprocessor design. The desire for increased performance has seen a push for deeper pipelines, as well as the introduction of pipelining schemes such as wave-pipelining and hybrid wave-pipelining. In this paper we present a hybrid wave-pipelined parallel adder that operates at 1.79 GHz, 42% performance improvement compared to that of a superpipelined adder. The simulations have been performed using a modest 0.25 mum technology. The three stage hybrid wave-pipelined parallel adder sustains a total of 8 unrelated data waves within the pipe. Another performance benefit achieved by using the hybrid wave-pipelining scheme is the lessening of delays associated with clock skew and clock distribution

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关键词

adders,delays,logic design,pipeline arithmetic,0.25 micron,1.79 GHz,clock distribution,clock skew,data waves,digital systems pipelining,high-performance parallel addition,hybrid wave-pipelining,microprocessor design,nonpipelined systems,superpipelined adder,three stage hybrid wave-pipelined parallel adder