High-Performance Scalable Multi-Node and Tiling Techniques for Accelerating 3D-FDTD on FPGAs

This paper presents a scalable FPGA-based architecture for the Finite-Difference Time-Domain (FDTD) method in computational electromagnetics. The proposed design addresses key limitations of existing FPGA accelerators, including on-chip memory constraints, external memory bandwidth bottle-necks, and limited multi-node scalability. The architecture combines synthesis-time tiling, fully pipelined dataflow execution, burst-based memory transfers, and optimized fixed-point arithmetic. The tiling strategy enables exact partitioning of the computational domain while fitting per-tile buffers within BRAM and URAM resources. The design is further extended to a multi-node cluster, where FPGA devices process independent sub-domains and exchange boundary data synchronously at each time step, enabling scalable parallel execution. Experimental results on an AMD Kria KV260 platform quantify the impact of each optimization in terms of performance, resource utilization, and efficiency, highlighting the trade-offs between memory usage and parallelism in FPGA-based FDTD accelerators.