Fully Homomorphic Encryption (FHE) introduces a novel paradigm in privacy-preserving computation, but operating on encrypted data imposes significant challenges, elevating data transmission, memory access demands, and programming complexity. Consequently, developing an efficient and usable system becomes vital. Conventional FHE accelerators often prioritize computational performance, typically assuming abundant encrypted data resides in accelerator memory. However, this perspective frequently overlooks the inefficiencies of the PCIe bus and main memory, alongside the complexities of optimizing for dedicated hardware in real-world deployments. This paper proposes Hypnos, a hardware/software co-design framework for memory-efficient homomorphic processing. The Hypnos framework pairs a novel processing unit architecture with a dedicated Hypnos Compiler. In architecture, the heterogeneous processing unit based on homomorphic encryption paging memory management system to reduce memory fragmentation and optimize the PCIe traffic. In software, the Hypnos compiler which is able to automatically translate high-level FHE schemes into optimized hardware commands. It schedules the data placement in cooperation with our memory management system to effectively harness the performance of hardware. This co-design of hardware and compiler not only reduces memory access and execution time but also lowers the complexity of deploying FHE applications. Finally, We implement Hypnos on the QianKun FPGA Card and highlight the following results: (1) outperforms SOTA ASIC and FPGA solutions in data-intensive applications by up to 2.75× and 4.72×; (2) the communication overhead is reduced by 4.85× compared to traditional architectures; (3) up to 30.1× and 20.7× energy efficiency improvement compared to ASIC-based ARK and FPGA-based Poseidon for ResNet-20 respectively.
原文链接
分享
引用
