Image Compression Using Approximate Addition

This paper investigates the application of approximate addition in digital image compression. Discrete cosine transform (DCT) is an important operation in digital image compression and we considered utilizing accurate addition and approximate addition separately while calculating the DCT. Accurate addition was performed using the accurate adder and approximate addition was performed using different approximate adders. Accurate and approximate adders were implemented in an ASIC design environment using a 32-28nm CMOS standard cell library and in a FPGA design environment using a Xilinx Artix-7 device. Error analysis has been performed to calculate mean absolute error and root mean square error of approximate adders by considering one million random input vectors. It is observed that approximate adders help to better reduce the file size of compressed images than the accurate adder. Simultaneously, the approximate adders enable reductions in design metrics compared to the accurate adder. For a FPGA implementation, an optimum approximate adder achieves 8% delay reduction and 19.7% power reduction while consuming 47.6% fewer LUTs and 42.2% fewer flip-flops compared to the accurate FPGA adder. With respect to an ASIC based implementation using standard library cells, an optimum approximate adder achieves 27.1% delay reduction, 46.4% area reduction and 50.3% power reduction compared to a high-speed accurate carry look-ahead adder.