Improving Trace Cache Processor Performance By Trace Cache Hierarchy And Path-Based Trace Prefetch

The performance of trace cache processor rests with trace cache efficiency to a great extent. Higher trace cache miss rate will reduce performance significantly because only a low fetch-bandwidth can be maintained by conventional instruction cache. Unfortunately, with the ever increasing conventional application scale, higher trace cache miss rate is inevitable for the relative small capacity of trace cache, which will become the bottleneck of performance improvement. In this paper, we proposed trace cache hierarchy to remedy the limited capacity of 1-level trace cache. 2-level trace cache is incorporated in trace processors. But the simulation results show that only augmenting 2-level trace cache can not bring significant performance improvement for the long access latency. So we propose a path-based trace prefetch mechanism to reduce the latency of 2-level trace cache access further. Path-based trace prefetch mechanism is developed on top of next N trace prediction mechanism. By predicting the next N trace from current and prefetching it into trace prefetch buffer from 2-level trace cache, the access latency of 2-level trace cache can be reduced. The simulation results show that augmenting an 8K-Entry, eight-way 2-level trace cache, an 16-Entry trace prefetch buffer and prefetch distance set to 3, the average IPC improvement is 12.0% for eight SPECint95 benchmarks.