Institute of Technical Sciences of the Serbian Academy of Sciences and Arts
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摘要
Detecting and correcting adjacent errors has become important in memory systems using high-density DRAM chips. The reason is that, in these systems, a strike by an energetic particle can upset one or more adjacent bits. In this paper, we present a simple solution for this problem based on integer codes capable of correcting/detecting burst errors within one byte and detecting double errors. Unlike the standard approach, in which the encoder/decoder is realized as a dedicated hardware block within the DRAM controller, the proposed method uses the processor as both the encoder and decoder. The effectiveness of this solution is demonstrated on a theoretical model of an eight-core processor. The obtained results show that the proposed method introduces a delay that is negligible compared to DRAM access latency, while enabling flexibility that is not achievable with conventional hardware-based solutions.