Intelligent Computing Framework for Board-Level Multi-Chip Thermal Design and Layout Optimization

This study proposes a hybrid optimization method for enhancing the thermal efficiency of on-board multi-chip systems, integrating target detection with machine learning algorithms. Experiments demonstrate that the Slimneck + EMA network adopted in the fusion stage achieves a 25.9% improvement in precision (P) and an 11.7% increase in Recall (R) compared to the original YOLOv8 algorithm, significantly enhancing target localization and component recognition efficiency. The research approach identifies chip variables with minimal impact on thermal dissipation through dimensionality reduction analysis, and predicts deviation by comparing temperatures across multiple post-fusion algorithms during layout optimization. Further analysis reveals that when the tolerance levels for the fitness function and constraint function reach 1e-6 and 1e-4 respectively, further increasing the iteration accuracy yields limited improvement in hotspot temperature optimization, with an enhancement rate below 0.85%. Validation via Nusselt number analysis confirms the thermally superior performance of the optimized chip layout under forced convection. The proposed optimization scheme achieves a 4% actual improvement over the Initial chip Layout, while the SVR-GA framework identifies an 8.4% theoretical optimization potential within the search space. This method effectively enhances the thermal performance of multi-chip circuit boards, providing an effective approach for high-power multi-device board-level design and thermal management.