Interface-Engineered Hafnia–MoS2 Ferroelectric Field-Effect Transistors Enabling a Nearly Ideal Memory Window with Back-End-of-Line Compatibility

Abstract Two-dimensional (2D) semiconductors, with their atomically thin geometry and excellent electrostatic control, are promising channel materials for ferroelectric field-effect transistors (FeFETs). However, integrating high-quality ferroelectric gate stacks onto these ultrathin channels in a manner compatible with modern semiconductor manufacturing, particularly under back-end-of-line (BEOL) constraints, remains a major challenge primarily due to interfacial instability. Here, we demonstrate interface-engineered top-gated 2D FeFETs based on monolayer molybdenum disulfide (MoS2) integrated with ferroelectric hafnium–zirconium oxide (HZO) via atomic layer deposition. An ultrathin high-κ yttrium oxide (Y2O3) interfacial layer serves as both a nucleation and protection layer, enabling conformal HZO growth while preserving a sharp van der Waals interface. All fabrication steps were conducted below 300 °C, fully satisfying BEOL thermal budgets. The resulting devices exhibit intrinsic polarization-driven switching rather than trap-dominant behavior. Notably, they achieve a nearly ideal memory window of 3.6 V, corresponding to ∼90% of the theoretical maximum, under a low operating voltage of ±3.5 V, along with distinguishable nonvolatile switching characteristics. These results establish a CMOS and BEOL-compatible interface engineering strategy for integrating high-performance 2D FeFETs, providing a scalable pathway toward monolithic 3D systems for future embedded memory and logic-in-memory applications.