Invited: Acceleration on Physical Design: Machine Learning-based Routability Optimization.

Design rule violation (DRV) is one of the significant challenges in designing integrated circuits. To successfully manufacture a chip, it is crucial to create a DRV clean layout. However, as technology nodes shrink and the cell density of the design increases, design rules have become increasingly difficult to meet, making the routing more complex. In addition, the conventional design flow has a problem in that it primarily determines design parameters and tool options, while evaluating routability at the end of the design flow. Furthermore, due to complex design rules, even global routers are not accurate enough, so routability can be assessed after actual routing, leading to significantly extended design turn-around times. In this paper, we introduce a framework that leverages machine learning techniques to overcome the limitations of the conventional design flows. We also present the challenges that arise during the construction of the framework, along with related research. Furthermore, we discuss issues that remain unresolved.