16-Layer 3D Stacking Based on Self-Assembly Technology for HBM Application

We address a trade-off issue between chip assembly time and positioning accuracy in a traditional pick-and-place method using self-assembly technology driven by liquid surface tension. This method allows 16-layer stacking of 50-mu m-thin chips fabricated via Plasma Dicing Before Grinding (PDBG). The surface tension of liquid droplets enables sub-50 nm alignment accuracy even with manual chip placement. By identifying key parameters such as pre-alignment position and liquid volume/distribution, we optimize the self-assembly process for High Bandwidth Memory (HBM) applications. Additionally, we discuss the effects of liquid bridges and wetting contrast between the chip surface and sidewall on multi-layer stacking.