Linearly Extensible System Based Interconnection Network for Multi-core Multi-Processor Systems

Multicore processor implementation for server, workstations and embedded multicore chips is a challenging task. The design decisions with underlying trends affect the performance of such systems. Conventionally, interconnection networks are designed to connect several nodes, each of them having different cores. However, the on-chip interconnection network between cores becomes a bottleneck as it is being shared by all the cores to cooperate while being solving a given problem. This paper presents a scalable Network-on-Chip architecture which exploits the interconnection network to connect different many core processors. The proposed architecture is designed in analogy to linearly extensible multiprocessor networks which have simple architecture and lesser cost. The introduced architecture is symmetrical in nature and exhibits the desirable properties of similar networks with lesser complexity and cost. A basic (4 x 4), 16-core architecture named as CA network is introduced which is symmetrically extendable at higher level with increasing number of cores. The topological variables such as number of cores, number of links, diameter and bisection width are evaluated for CA network and a comparative study is carried out with Mesh and Torus networks in order to validate the ascendancy of the proposed architecture. The proposed CA network has low diameter, low cost and performs better with lesser number of nodes. It is scalable and expandable easily at higher levels with lesser complexity.