LiveFIFO: FPGA-in-the-Loop Buffer Sizing for Dataflow Accelerators

Sizing intermediate data buffers has been a long-standing challenge in building FPGA dataflow accelerators. Current techniques rely on imperfect analytical models or time-intensive simulation, often choosing suboptimal buffer sizes, which either waste valuable resources or risk performance degradation. We introduce an FPGA-accelerated buffer-sizing approach that finds locally optimal first-in-first-out (FIFO) buffer sizes by synthesizing and profiling a lean but faithful surrogate of the target dataflow design. Contrary to existing simulation-based or model-based techniques, our approach guarantees optimal throughput and latency results using a search-based fine-tuning step, which is enabled by our ability to evaluate any FIFO depth configuration five orders of magnitude faster than in simulation. We fully integrate our approach into the open-source deep neural network (DNN) accelerator compiler FINN and evaluate it on a suite of 12 example DNNs, achieving a total FIFO size reduction of up to 86