Low Latency Binary Edward Curve Crypto Processor for FPGA Platforms

Elliptic Curve Cryptography (ECC) offers a highly effective and suitable method for implementing public keys in environments with limited resources. The Edwards curve solves the unifiedness and completeness problems with elliptic curves. A scalar multiplication operation is essential to crypto-processors based on curves. This study presents a distinctive FPGA implementation of a Binary Edwards Curve (BEC) cryptographic processor that enhances scalar multiplication through parallelization. The method significantly reduces clock cycle usage by employing multiple hybrid Karatsuba multipliers specifically two and a parallelized Hex Itoh-Tsujii algorithm for field inversion. The suggested architecture further improves resource sharing between point operations and field inversion, resulting in higher throughput over area efficiency. The proposed architecture performs 233-bit point multiplication on Virtex-4 and Virtex-7 platforms, achieving latencies of 0.033 ms and 0.025 ms, respectively, setting new performance benchmarks. This results in a 13