Memory ECC Logic Testing Using MBIST

Memories with Error Correction Codes (ECC) are essential for high-safety and high-reliability applications. Ensuring the integrity of ECC logic requires thorough testing during both manufacturing and in-system operation. While scan patterns are effective for ECC testing in manufacturing, they are unsuitable for in-system tests. Additionally, the ECC deep XOR tree structure leads to lengthy scan test pattern generation time. Although standard Memory Built-In Self-Test (MBIST) techniques are employed in both manufacturing and in-system tests, they provide limited fault coverage for ECC logic. This paper proposes a novel method for comprehensive ECC functionality testing, leveraging enhanced MBIST patterns with integrated fault injection capabilities. This approach offers a significant advantage by requiring only minimal modifications to existing MBIST hardware, without altering the memory or ECC design. Experimental results demonstrate high fault coverage for both stuck-at and transition faults on par with scan patterns. The method offers flexible deployment, applicable either independently or in conjunction with scan patterns for manufacturing testing, and independently for in-system testing, thereby significantly enhancing the overall quality assurance of ECC logic.