Model Predictive Zero-Sequence Circulating Current Suppression for Grid-Connected Parallel Inverters with Switching Sequence Reorganization

The zero sequence circulating current (ZSCC), comprising both low-frequency (LFCC) and high-frequency (HFCC) components, significantly degrades the efficiency and reliability of grid-connected parallel inverter systems. However, constrained by fixed switching sequences, conventional communication-free methods fail to simultaneously suppress such multifrequency disturbances. To address this issue, this article proposes a communication-free switching sequence reorganization-based model predictive circulating current suppression (SSR-MPCCS) strategy. First, the generation mechanisms of ZSCC are analyzed mathematically, revealing that LFCC stems from the monotonic accumulation induced by the consistent polarity of average common-mode voltage (CMV) differences over multiple switching cycles, whereas HFCC originates from instantaneous CMV differences within a switching period. Second, to suppress LFCC, a dynamic sequence reorganization scheme is proposed. By reconfiguring the vector arrangement according to the ZSCC polarity, the monotonic accumulation trend is effectively disrupted. Finally, for HFCC suppression, a duty cycle redistribution scheme is proposed. This scheme dynamically adjusts the duration of zero vectors u 0 and u 7 based on estimated maximum fluctuations, thereby preventing spikes triggered by excessive instantaneous CMV differences. The effectiveness of the proposed method is demonstrated by the experimental results.