Parallel Protocol Implementations for High Speed Networks

M ZITTERBART

SBT/IEEE International Symposium on Telecommunications (IST)（2002）

Inst. of Telematics

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摘要

The development of high speed networks with data rates of 100 Mbit/s and more as well as the design of advanced applications imposes new requirements on the performance of network nodes. The author describes an approach to overcome the upcoming processing bottlenecks of communication protocols. The approach is based on the use of multiprocessor architectures. Several parallel concepts inside network nodes such as pipeline and array constructs are outlined, and different memory concepts are suggested. Performance measurements of protocol implementations on transputer networks following the proposed parallel concepts indicate very promising performance results.<>

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关键词

parallel architectures,protocols,transputers,100 Mbit/s,array constructs,communication protocols,data rates,high speed networks,memory,multiprocessor architectures,network nodes,parallel protocols,performance measurements,pipeline constructs,processing bottlenecks,transputer networks