Processor Arrays

In this paper we will present new adaptive routing algorithms for faulty processor arrays. Past research has shown that packet switched based communication performance in mesh connected networks is significantly degraded by the presence of faulty processors. Nondeterministic routing algorithms have been developed based on transport modeling of packet flow in disordered arrays. By utilizing nondeterministic routing strategies, based on biased random walkers, we can implement deadlock free routing, at the expense of not following the shortest path. These algorithms will be shown to be capable of increasing network bandwidth in the presence of faulty processors and interconnects. These algorithms offer an alternative to conventional adaptive routing techniques by utilizing a computationally simple algorithm based on local (nearest neighbor) information. Although we concentrate our efforts on 2 dimensional processor arrays, the algorithm are also suitable for higher dimensional topologies such as hypercubes.