Provably Good Physically Aware WRONoC Design for Customized and Fault-Tolerant Topologies with Parallel Switching Elements and Sequence-Based Models

The wavelength-routed optical network-on-chip (WRONoC) is a promising solution for system-on-chip designs. Recent work in the WRONoC topology designs mainly utilizes crossing switching elements (CSEs) as switching mechanisms on predefined templates. However, using CSEs incurs more microring resonator (MRR) usage and waveguide crossings than parallel switching elements (PSEs), and their predefined templates constrain the solution spaces. To remedy these disadvantages, we propose a fully automated topology design flow that utilizes PSE structures to reduce MRR usage and waveguide crossings. Our add-drop filter sequence model expands the solution space and leverages the advantage of the crossing-free PSE structure. With the sequence model, we also derive lower bounds of the MRR usage and the maximum insertion loss for the topology. For full-connectivity topologies, our proposed flow guarantees optimal (minimum) MRR usage. Our fixed-node crossing-aware edge routing effectively minimizes waveguide crossings, and our A*-search preserves the admissibility property and guarantees an optimal routing solution. Besides, our design flow thoroughly considers the information from the physical layout. Experimental results show that our design substantially outperforms state-of-the-art works on customized designs.