Pyls: Enabling Python Hardware Synthesis with Dynamic Polymorphism Via LCRS Encoding

Python dominates AI development and is the most widely used dynamic programming language, but synthesizing its polymorphic functions into hardware remains challenging. Existing HLS solutions support only static subsets of Python, forcing CPU offload with costly communication overhead. We present PYLS, the first framework that synthesizes dynamically polymorphic Python into monolithic hardware via Left-Child Right-Sibling (LCRS) encoding. Key to our approach is representing all Python objects as LCRS trees, enabling uniform hardware handling of dynamic types. PYLS automatically converts objects to fixed-width formats, generates XLS IR designs, and implements a tree memory architecture for efficient runtime type resolution. On FPGA platforms, PYLS demonstrates speedups of 5.19x and 3.98x over two ASIC CPUs, 303.29x over a soft-core processor, and 282.66x over a heterogeneous SoC design.