Real-Time RISC Processing

In real-time computing the correctness of the system depends not only on the logical result of the computation, but also on the time at which the results are produced. Thus, much of real-time computing relies on predicting worst-case execution times (WCET). The increasing computational demands of today''s real-time systems require architecturally advanced processors be used. These advanced processors must have a TLB, cache memory, memory write buffer, out-of-order execution, branch prediction, deep pipelines, and multiple functional units. While these high performance architectural features enhance the average performance, they can add considerable variance to the WCET predictions of programs. The first section of this paper discusses how to incorporate advanced processor features while maintaining tight WCET predictions; the tradeoff is a slight loss in performance for lower variability. We show how a design for real-time can co-exist with a traditional design as a software mode that can be selected dynamically. The second section compares RISC processors and digital signal processors (DSPs) as to their real-time strengths and weaknesses and we estimate the design effort to correct their respective weaknesses. We conclude that current RISC processors match real-time processing needs much more closely than current DSPs.