Dataflow-based coarse-grained reconfigurable architectures (CGRAs) and dynamic high-level synthesis (DHLS) are both promising for accelerating applications with nontrivial control and memory behavior, but existing compilation flows are typically fragmented and often struggle with control handling, memory ordering, and effective resource reuse. In particular, prior CGRA compilers are still limited in compiling control-rich programs, while existing DHLS flows are not well aligned with dataflow CGRA compilation. This paper presents RedPanda, a unified compilation frame work for both dataflow-based CGRAs and DHLS. The main contribution of RedPanda is a shared front- and middle-end built on a common RedPanda IR, which enables the two targets to reuse the same core compiler infrastructure. On top of this foundation, RedPanda introduces static analyses and transformations for branch handling, memory ordering, aggressive loop pipelining, and time-multiplexing-aware compilation, thereby improving support for control-/memory-irregular workloads while reducing unnecessary serialization and instruction overhead. After this shared compilation stage, the IR is lowered to target-specific back-end flows for CGRA mapping and DHLS circuit generation. Experimental results show that RedPanda reduces CGRA spatial execution cycles by 33.4%, improves temporal-CGRA resource efficiency by 37%, and reduces instruction count by about 13%. For HLS, RedPanda achieves at least 34% faster execution while using fewer LUT, DSP, and FF resources. These results demonstrate that RedPanda provides a practical unified compilation foundation for both CGRA and DHLS targets.
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