Reversible integer-to-integer wavelet transforms for image compression : implementation and evaluation

There has been a growing interest in the reversible integer to integer wavelet transforms for image coding. In this paper, several of those particular transforms are integrated using a VHDL description on a FPGA circuit. Two different architectures are proposed, one uses the lifting framework as an architectural support and the other takes advantage of the two finite impulse response filter (FIR) structures representing the wavelet transform function. Evaluation is performed on the basis of their computational complexity, latency, hardware occupancy, and finally maximum operating clock frequency of the circuit obtained. Of the transforms considered, some of them seem to perform particularly well depending on the architecture used.