Rowhammer for Spin Torque Based Memory: Problem or Not?

Summary form only given. Rowhammer is a known security vulnerability in recent Dynamic Random Access Memory (DRAM) devices, where repeated access to an array of memory can flip the bits in the adjacent row owing to the charge leakage/ capacitive coupling. Several studies have documented the Rowhammer effect [1, 2]and Google's project zero demonstrates two working examples of a security exploit [3]. Furthermore, many published scenarios highlight that scaled DRAM below 32nm [1]is exposed to potential hacking attacks because of the Rowhammer problem [3], owing to reduced spacings in DRAM bits. Thus, it is only natural to test any new upcoming technology for a similar problem. Though the working mechanisms of DRAM and spin transfer torque magnetic random access memory (STT-RAM) are drastically different, whether the STT-RAM is also potentially vulnerable to an analogous Rowhammer effect or not is not documented or discussed in literature. While the mechanism of failure is high enough charge leakage in DRAM, the corresponding mechanism in STT-RAM may be the lowering of the thermal barrier because of the dipolar magnetic field exerted by adjacent selected bits. The lowering of the thermal barrier in turn can increase the probability of an erroneous bit flip. To ascertain whether the effect is substantial, nearest (A bit) and next nearest neighbour bits (B bit) adjacent to an unselected bit (O bit) are simulated as shown in Fig 1. The bit diameter is 55nm and the center to center bit spacing is 200 nm. The magnetic field at the O bit is simulated, when all the A and B bits have been assumed to have the magnetization pointing in the same direction. While this configuration does not necessarily conform to the conventional idea of selecting an adjacent row of bits or even both the adjacent rows (double sided hammering), it provides a scenario where the most favorable conditions for an erroneous bit flip can be evaluated in STT-RAM. Three magnetic layers are assumed in each bit separated by appropriate non-magnetic regions corresponding to the STT-RAM stack. The top most layer corresponds to the Free layer (FL) and can be flipped while the others are held fixed. While calculating the magnetic field at the O bit, the middle layer is assumed to have a magnetization opposite to the topmost and bottom layers. The other configuration in which the topmost layers is flipped and is parallel to the middle layer is known to give a smaller magnetic field. A magnetostatic calculation is done to determine the magnetic field at the site of the FL layer of the O bit. The average of the field over the entire volume of the O bit is evaluated as a function of bit spacing using magnetostatic calculations as shown in Fig 2. For the largest bit spacing of 200 nm the simulated field is only around 7 Oe while for a 100nm bit spacing it increases to 60 Oe. The analytical calculation assumes each magnetic layer in each bit to be a point. The vector sum of all of these at the location of the O bit is shown here. The discrepancy between the simulated and the analytical results increases as the bit spacing decreases. This is because of the assumption that each layer is assumed to be a point. To assess the impact of these fields, the string method is used to evaluate the energy barrier between two magnetic states corresponding to 0 or 1 stored on the O bit. Inset of Fig 2shows that for a field of 7 Oe the change in energy barrier is less than 1 kT which is not large enough to cause an appreciable change in the bit error rate. For example based on Eqn 18 of [4] the bit error rate will only double for a 1 kT change in energy barrier assuming a retention time of 10 years and a relaxation time of 1 ns. Even for a bit spacing of 150 nm the increase in the BER will be less than an order of magnitude. However for a smaller bit spacing of 100 nm the BER can go up by 3 orders of magnitude. Therefore, as it stands rowhammer effect in STT-RAM does not appear to be appreciable at the 200 nm bit spacing. However at lower bit spacings the effect might become prominent and would require additional design rules to circumvent. As in the case of DRAM different techniques might have to be adopted to mitigate the problem.