Securing IJTAG with Dynamic Priority Control and Path-Integrated Validation

The reconfigurability of IEEE 1687 (IJTAG) enhances test flexibility but also exposes scan paths to security threats such as data sniffing, tampering, and unauthorized access. To mitigate these risks, this paper presents a two-tier secure IJTAG architecture that combines dynamic priority arbitration with a parallel CRC (Cyclic Redundancy Check)-protected scan core. The arbitration module restricts scan participation to instruments with valid configuration bits and priority tokens, providing fine-grained access control. However, while effective against unauthorized access and path manipulation, it cannot detect data tampering. To address this, lightweight checksums are appended at scan-in and verified at scan-out to detect data modifications. Together, these mechanisms block a wider range of attacks and ensure end-to-end scan data integrity. Simulations show that the architecture effectively prevents attacks such as data sniffing and tampering, even when malicious instruments are embedded within the scan path. When implemented in 65 nm CMOS technology, the design incurs less than 35% area overhead, offering robust security with minimal impact on IJTAG compatibility and performance.