Semiconductor Scaling Via Self-Aligned Block Patterning

Since its first appearance in 1965, Moore’s law (i.e., the observation that the density of transistors on integrated circuits doubles approximately every two years) has survived many threats to its perpetuity. In fact, it has thrived for the past 20 years.1, 2 With the semiconductor industry on the cusp of the N5 (5nm) technology node, however, this status quo is changing, and— as has been announced by many integrated-device manufacturers and foundries3, 4—areal scaling is approaching a slowdown. One of the key factors to overcoming this slowdown lies in obtaining control over the variability that creeps in during fabrication, leading to yield degradation.5 In patterning, this variability has been quantified as the edge-placement error (EPE). Simply defined, the EPE is the difference between the intended design and the actual on-silicon results. Controlling EPE at N5 and beyond is one of the foremost challenges for semiconductor fabrication. In the development of advanced technology nodes, interconnects in integrated circuits represent a major area for which EPE control is a key factor.5 Critical back-end-of-the-line (BEOL) trench patterning at the N5 node requires a sub-30nm pitch line-space pattern. This small pitch (i.e., center-to-center distance between features) can be achieved using high volume manufacturing (HVM)-ready 193nm immersion-lithography-based self-aligned quadruple patterning (SAQP). However, block patterning (i.e., cutting an as-generated grid into a desired pattern) remains a challenge in terms of EPE. The standard approach for block patterning is shown in Figure 1. For both 193nm immersion-based and 13.5nm extreme UV (EUV)-based block patterning, multiple bright-field pillar-mask-based lithography passes are required (i.e., 4–5 and 2–3 masks, respectively). At the N5 node, this approach is challenging due to two major issues. Figure 1. (a) Traditional block-mask approach for critical back-end-ofthe-line trench patterning on a line grid defined by spacers (i.e., material A). Vertical gray and white lines show the eventual locations of dielectric material and metal wires, respectively (i.e., after metallization). The pink ellipse represents the block mask. Transparent ellipses show examples of bad overlay (with respect to the trench). In such cases, the block mask may cause electrical short circuits. (b) Our multicolormaterial-based approach, in which each color designates a different etch selectivity. In our approach, every other trench is filled with a different sacrificial material (i.e., B and C, which would be a spin-on metal and a type of silicon, respectively). By introducing alternate materials in each trench, overlay variation is made trivial. Based on our calculations, this approach reduces the negative effects of overlay by three times compared to the approach shown in (a).