Software and Hardware Processing Method for Blockchain Light Node SPV Verification

With the application of blockchain light nodes in embedded devices, how to alleviate computing pressure brought by complex operations such as transaction’s SPV Verification for CPU of embedded devices and improve the performance of devices in these aspects has gradually become a research topic in industry and academia. This paper proposes a series of methods to improve the performance of blockchain SPV Verification from the perspectives of system architecture and hash computing unit: (1) According to the computational characteristics of SPV Verification, this paper customizes macro instructions and microinstructions for the coprocessor to meet the requirements of flexibility; The built-in dedicated cache holds transaction data fetched from external memory and intermediate data generated by internal Hash Computing Unit, which not only prepares transaction data for hash computation, but also avoids frequent access to the bus and external memory. (2) Techniques like two-round unfolded computing, timing-balanced pipeline architecture and optimized adders are adopted to improve the performance of SHA256 computation. (3) When double hash computing is required for transactions, Hash Computing Unit can directly perform the second hash computation based on the first hash computation, reducing the frequency of accessing to external memory, thereby improving the performance to a certain extent. Through these methods, the performance of the hardware coprocessor for SVP verification of transactions is more than double that of traditional solutions.