Sustainability Framework for Computing Element Design

The semiconductor industry has revolutionized information and communication technologies by enabling unprecedented advancements in computing, communication, and automation. However, alongside this rapid progress, the escalating power consumption and resource demands of integrated circuits have raised critical sustainability concerns. Traditional evaluation figures of merit, such as Power, Performance, and Area (PPA), no longer appear to be sufficient enough to address the environmental impact of these designs. Hence, there is a need for an evaluation paradigm that can assess a design based on Power, Performance, Area, and Sustainability (PPAS). This research proposes a novel Sustainability Framework to allow designers to assess, benchmark, and choose the most efficient and environment-friendly architecture for their product development at the early design phase (i.e., ‘schematic’ and ‘layout’). The proposed framework is applied on a wide variety of foundation cells to demonstrate it’s wide applicability and agility. Foundation cells have been benchmarked and the impact of design choices on sustainability is presented based on different applications like IoT, Automotive, High-Performance Computing, and Portable Electronics.