SystemC/TLM Flow for SoC Design and Verification

As systems grow in complexity, their verification becomes a bottleneck on the design flow. In this paper we propose a top-down methodology to perform the complete flow from specifications to Register Transfer Level (RTL). Different abstraction levels such as Transaction Level Modeling (TLM) allows early system verification (with simulation or formal methods), reducing the risk of long redesign cycles. The methodology is validated by showing a case study.