Targeted TEM SRAM-Like Analysis Without Delayering

Abstract In the ever-increasing complexity of today’s state-of-the-art semiconductor structures, it is desirable to seek any advantage in the fault isolation and analysis paradigm to improve time to data. This paper discusses one such improvement where it is shown to be possible to target silicon (Si) devices, their metal contacts, or any other location in the wafer stack in a SRAM test structure from metal level 7 (M7) for transmission electron microscopy (TEM) sample fabrication using a modified sample geometry, focused ion beam (FIB) software targeting tools, and planning for failure analysis at the mask design stage. Electron beam inspection data was used to drive back to the location of interest in this example. The subsequent analysis shows a silicon and oxygen rich material creating an open contact defect signature.