The internal architecture of a 2000 MIPS/1000 MFLOPS (peak) high-performance low cost CMOS Alpha micro-processor chip is described. This implementation is derived from the Alpha 21164 microprocessor to reduce cost while maintaining high performance. It contains a quad-issue super-scalar instruction unit, two 64-bit integer execution pipelines, and two 64-bit floating point execution pipelines. The memory unit and bus interface unit have been re-designed to provide a high performance memory system using industry standard PC SRAM and DRAM components.