Variable Precision Computing

Jeffrey Hittinger, P. Lindstrom,H. Bhatia,P. Bremer, D. Copeland, K. Chand, A. Fox, G. Lloyd,H. Menon, G. Morrison, D. Osei-Kuffuor, N. Pinnow, D. Quinlan, G. Sanders,M. Schordan, T. Vanderbruggen, D. Hoang, P. Klacansky, V. Pascucci,W. Usher, M. Lam, L. Moody, J. Diffenderfer,A. Metere, L. Yang

crossref（2019）

Lawrence Livermore National Laboratory (LLNL)

被引用3|浏览6

摘要

provides power to bit slices in the arithmetic logic unit and a clock signal generator provides clock signals to the bit slices. Gate logic is configured to gate the power or the clock signals provided to a subset of the bit slices.

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关键词

Feedforward Neural Networks

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