[0001]Cross-referencing of related applications This application claims priority, 26 December 2017 which @datdatdate@ filed Korean Patent No. 10 - 2017-0179851, the entire contents of which are hereby incorporated by reference in their entirety. The technical field is. Embodiments of the present invention relate to integrated circuit chips. Background technology With the great progress in semiconductor memory technology, the packaging technology of semiconductor devices also requires high integration and high performance. Thus, a technique regarding a three-dimensional (3D) structure for vertically stacking a plurality of integrated circuit chips instead of a two-dimensional structure is being developed in various ways. To a two-dimensional structure, the integrated circuit chip is planarly arranged on a printed circuit board (PCB) using wires or bumps. The three-dimensional structure may be implemented in the form of a stacked memory device in which there are a plurality of memory chips stacked one above another. The memory chips stacked in the vertical direction are electrically connected to each other through a through silicon via (TSV) and mounted on a substrate. Summary of the invention The embodiment of the invention relates to a technology for effectively testing an integrated circuit chip. To one embodiment of the present invention, the invention is further described. An integrated circuit chip comprising: one or more couplers adapted to transmit data between stacked chips; one or more data nodes adapted to transmit data between the one or more couplers and the one or more data nodes, wherein at least one of the one or more transmission circuits invert a portion of the data transmitted by the at least one transmission circuit . and wherein, the at least one transmission circuit is configured to transmit data between the one or more data nodes. To another embodiment of the present invention, the present invention is not limited thereto. An integrated circuit chip, comprising: first coupler and second coupler adapted to couple data between stacked chips; first a transmission circuit adapted to convert data of the first coupler and the second coupler in parallel to produce first conversion results and transmit the first conversion result to first data transmission lines, wherein a portion of the data of the fourth coupler and the first coupler is inverted and transmitted 2nd; and a transmission circuit, for example. The second Transmission circuitry adapted to perform parallel to serial conversion of data of said first data transmission line to fourth data transmission line to produce second conversion results and transmit said second conversion results to fifth data transmission lines and 6th data transmission lines; and 333 transfer circuitry adapted to perform parallel to serial conversion of data of said first data transmission line and said fourth data transmission line to generate third fifth conversion results and transmit third said 6th conversion results to data nodes. To yet another embodiment of the present invention, there are provided. A memory device comprising: a base die including one or more data nodes for transmitting data to and receiving data from a host and one or more core dies stacked over the base die, transferring data to and from the base die through the one or more transmission lines. and one or more core dies stacked over the base die. The substrate die is configured to receive data, and transmit data to and from the host die. A cell array for storing data, wherein the base die comprises one or more transmission circuits on a transmission path for transmitting data from the one or more couplers to the one or more data nodes, and at least one of the one or more transmission circuits inverts a portion of the data transmitted by the at least one transmission circuit. Yet another embodiment according to the present invention, is provided. An integrated circuit chip comprising: at least one coupler adapted to transmit and receive data between at least two stacked chips; at least one data node adapted to transmit data to a host; and at least one transmission circuit adapted to convert and transmit data on the transmission path, wherein the data on the transmission path is serially converted or parallel to a serial conversion and a portion of the data on the transmission path is inverted. Description of the drawings 1 Is a block diagram illustrating a storage system according to one embodiment of the present invention. 2 Is a block diagram illustrating a base die of a memory device, according to an embodiment of the present invention; base die) is provided. 3 Is a timing diagram illustrating a test procedure of a write operation of a base die according to one embodiment of the present invention. 4 And 5 are timing diagrams illustrating a test procedure of a read operation of a base die according to one embodiment of the present invention. 6 Is a block diagram illustrating first transmission circuits in accordance with one embodiment of the present invention. 7 Is a timing diagram illustrating a data strobe signal and first strobe signals to 8th strobe signals according to one embodiment of the present invention. 8 Is a block diagram illustrating second transmission circuits in accordance with one embodiment of the present invention. Specific implementation Embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. However, the present invention may be embodied in different forms and should not be construed as being limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the invention to those skilled in the art. The disclosure, like reference numerals refer to like parts throughout the various figures and embodiments of the invention, refer to like parts. It is to be noted: the mentioned "one embodiment" does not necessarily mean just one embodiment, for example. The "one embodiment" mentioned at a different point does not necessarily refer to the same embodiment. It will also be understood, when an element is referred to "as being ' connected" or "coupled" to another element, it can be directly on another element, to or coupled to another element, or one or more intervening elements may be present. In addition, it is also to be understood, when an element is referred to as "between two elements", it can be the only element between the two elements, or one or more intervening elements may also be present. The terminology used herein is for the purpose, and is not intended to be limiting of the invention. As used herein, the singular forms may equally include plural forms, and vice versa, unless the context clearly dictates. In the following, various embodiments of the present invention will be described in detail with reference to the accompanying drawings. 1 Is a block diagram illustrating a memory system 100 in accordance with one embodiment of the present invention. To FIG. 1, the memory system 100 may include a memory device 110, a memory controller 120, an interposer 130, and a package substrate 140. The interposer 130 may be formed in a portion above the package substrate 140, for example. The memory device 110 and the memory controller 120 may be formed in the upper portion of the interposer 130. Since the memory controller 120 is typically included in various processors such as a central processing unit (CPU), a graphics processing unit (GPU), and an application processor (AP), the memory controller 120 may also be referred to as a processor. The interface PHY of memory device 110 and the interface PHY of memory controller 120 may be coupled through interposer 130, respectively. An interface for communication between the memory device 110 and the memory controller 120 is referred to as PHY. The memory device 110 may be formed to stack the plurality of integrated circuit chips and electrically connect the integrated circuit chip through a silicon via (TSV), for example. The integrated circuit chip may include a base die 114 and a plurality of core die 112. Each of the core dies 112 may have a cell array for storing data and a circuit for reading data from the data write cell array and the slave cell array. A circuit for interfacing between the core die 112 and the memory controller 120 may be disposed on the base die 114. When the memory device 1 10 时 is formed in this manner, the number of input/output units may be greatly increased, which facilitates increasing the bandwidth. By way of example, and not limitation, memory device 110 formed as described above may be a high bandwidth memory (HBM). 2 Is a block diagram illustrating a base die (e.g. a base die 1 of the memory device 110 shown in FIG. 114) of a memory device in accordance with an embodiment of the present invention. 2 Shows only a portion that is directly related to the data transfer in the substrate die 114, for. To FIG. 2, base die 114 may include coupler TSVSVR and TSVSVR, data node DQ, first transmission circuit 210, second transmission circuit 220, third transmission circuit 230, fourth transmission circuit 240, fifth transmission circuit 250, and 6th transmission circuit 260. The data node DQ may be a node for transmitting/receiving data to/from the host (i.e. the memory controller 1 of FIG. 120). The data node DQ may be coupled to the mini-bump for coupling to the interposer 130, and may then be coupled to the interface PHY of the memory controller 130 through the interposer 120, for example. In the interface PHY region of the base die 114, there may be hundreds of thousands of data nodes DQ. In FIG. 2, only one data node DQ is shown. The first Couplers TSVSVR and second couplers TSVSVF may be chips (i.e. chips) for being stacked on a base die 114. The core die 112) transmits and receives data together with a node. Each coupler in coupler TSVSVR and coupler TSVSVF may be coupled to a silicon via (TSV). The base die 114 may have a plurality of couplers TSVSVR and TSVSVF, while only couplers TSVSVR and TSVSVCs corresponding to one data node DQ are shown in FIG. 2. The first Transmission circuit 210, second transmission circuits 220, and third transmission circuit 230 may be circuits for transferring data from coupler TSVSVR and coupler TSVSVF to data node DQ. The first Transfer circuits through third transfer circuits 210,220, and 230 may be used to transfer data read from core die 112 to memory controller 120 during a read operations. The first Transmission circuit 210 may transfer data first coupler TSVSVR data from second coupler TSVSVF to first data transmission lines TIOIORL, to fourth data transmission lines TIORL. TIOFOFL, TIOIORH, and TIOFOFH. The first Transmission circuit 210 may serialize data of first coupler TSVSVR with second coupler TSVSVF data in @timetime@ (2:4 i.e. @timetime@) 1:2 to parallel conversion, and then output the results to first data transmission line TIOIORL, fourth as a result. TIOFOFL, TIOIORH, and TIOFOFH. The second Transmission circuit 220 may convert data of first data transmission lines to fourth data transmission lines TIOIORL, TIOFOFL, TIOIOHs, and 4:2 TIOFOFs to serial 2:1 conversion in @timetime@ (i.e. @timetime@), and then transfer the results to fifth data transmission line MIOR and 6th data transmission line MIOF. The third Transmission circuit 230 may transmit data of fifth data transmission line MIOR and data 6th data transmission line MIOF to 2: 1 Proceeds to serial conversion, and then transfers the result to data node DQ. The fourth Transmission circuit 240, fifth transmission circuits 250, and 6th transmission circuit 260 may be circuits for transmitting data from data node DQ to coupler TSVSVR and coupler TSVSVF. The fourth Transfer circuitry to 6th transfer circuits 240,250 and 260 may be used to transfer write data transferred from memory controller 120 to core die 112 during a write operation. The fourth Transmission circuit 240 may log data of data node DQ in 1: 2 Proceeds to parallel conversion, and then transfers the results to fifth data transmission line MIOR and 6th data transmission line MIOF. The fifth Transmission circuit 250 may serialize data of fifth data transmission line MIOR and data 6th data transmission line MIOF to 2:4 parallel conversion in 1:2 (i.e. @timetime@) to transmit the results to first data transmission lines TIOIORL, TIOFOFL fourth and the like. TIOIOs and TIOFOFs. 6th Transmission circuit 260 may convert data of first data transmission lines to fourth data transmission lines TIOIORL, TIOFOFL, TIOIOHs, and 4:2 TIOFOFs to serial 2:1 conversion in @timetime@ (i.e. @timetimeplus), and then transmit the results to first couplers TSVSVR and second couplers TSVSVF. The base die 110 of the memory device 114 and the core die 112 may be separately fabricated, for example. The coupling. In this case, they have to be individually tested before they are coupled together. Thus, the substrate die 114 may also be tested before the base die 112 is coupled to the core die 114. To improve test efficiency of the base die 114, the path from coupler TSVSVR and coupler TSVSVF to data node DQ can be designed to invert and transmit a part. In other words, at least one of the transmission circuits 114 and 210,220 on the path through which the read data transmitted from the base die 230 is transmitted may be designed to invert and transmit a part. For example, first transmission circuits 210 and second transmission circuits 220 may be designed to invert and transfer portions. To 3 through 5, at least one of the transmission circuits 210,220 and 230 causes a portion of the data transmitted by the transmission circuits 210,220 and 230 to be inverted, as will be explained. The base die 114 may perform the test procedure shown in 112 through 3 separately without coupling with the core die 5. 3 Is a view illustrating a base die (e.g. a substrate) according to one embodiment of the present invention. FIGS. 2 are timing diagrams of a test procedure of a write operation of the substrate die 114). To FIG. 3, the eight data 0 through 7 input to the data node DQ can be serially connected 1:2 in parallel by @timetime@ to fifth data transmission line MIOR and 6th data transmission line MIOF. The data of fifth data transmission line MIOR and the data 6th data transmission line MIOF 1:2 can be serially converted in parallel by @timetime@ and transmitted to first data transmission lines TIOIORL, to fourth data transmission lines. TIOFOFL, TIOIORH, and TIOFOFH. Data first data transmission lines to fourth data transmission lines TIOIORL, TIOFOFL, TIOIORH, and TIOFOFH may 2:1 be transmitted in parallel to serial in @timetime@ and transmitted to first couplers TSVSVR and second couplers TSVSVF. 4 Is a view illustrating a base die (e.g. a substrate) according to one embodiment of the present invention. FIGS. 2 are timing diagrams of a test procedure of a read operation of the substrate die 114). The process of FIG. 3 may be performed subsequent to the process of FIG. 4. In FIG. 4, it is assumed that both the transmission circuits 210,220 and 230 do not perform the operation of inverting part of the data. To FIG. 4, it can be seen: data 6 is continuously loaded onto first coupler TSVSVR, while data 7 is continuously loaded onto second coupler TSVSVF. Because only the base die 114 (and the coreless die 112) performs a read operation after the write operation is performed, only the last written data 6 and data 7 are left in first coupler TSVSVR and second coupler TSVSVF during the write operation, respectively. When the read operation is performed in this case, only data first and data second left in 6 coupler TSVSVR and 7 coupler TSVSVF can be transmitted to first data transmission line to fourth data transmission line TIOIORL, respectively. TIOFOFs, TIOIOs, and TIOFOFs, are then transferred to fifth data transmission line MIOR and 6th data transmission line MIOF. In this case, since only a very single data pattern is transmitted to first transmission line to 6th transmission line TIOIORL, TIOFOFL, TIOIORH, TIOFOFH, MIOR, and MIOF, it may be difficult to verify whether first transmission circuits 210 through third participating in 230 the read operation normally operate. In particular, it is preferred. Since only the same data is loaded to first data transmission lines to 6th data transmission lines TIOIORL, TIOFOFL, TIOIOHs, TIOFOFH, MIOR, and MIOF, it is difficult to verify whether first transmission circuits 210 220 and second transfer data normally. 5 Is a view illustrating a base die (e.g. a substrate) according to one embodiment of the present invention. Timing diagram of the testing process of the read operation of the substrate die). 114The process of FIG. 3 may be performed subsequent to the process of FIG. 5. In FIG. 5, it is assumed first transmission circuits 210 and second transfer circuits 220 perform operations that invert a portion of the data to be transmitted to improve test efficiency. To FIG. 5, it can be seen: data 6 is continuously loaded onto first coupler TSVSVR, while data 7 is continuously loaded onto second coupler TSVSVF. Because only the base die 114 (and the coreless die 112) performs a read operation after the write operation is performed, only the last written data 6 and data 7 during the write operation may be left in first coupler TSVSVR and second coupler TSVSVF, respectively. The first Transmission circuit 210 may invert a portion of data transmitted by first transmission circuit 210, and transfer the inverted data to first data transmission line TIOIORL, to fourth data transmission lines. TIOFOFL, TIOIORH, and TIOFOFH. Thus, unlike FIG. 4, in FIG. 5, data other than the same data but switching patterns may be continuously loaded on first data transmission lines to fourth data transmission lines TIOIORL, TIOFOFL, TIOIORH, and TIOFOFH. In FIG. 5, the data with the skimming (') may represent the inverted data. For example, data 6 'may represent the inverted data 6' and data 7' may represent the inverse data. 7. The second Transmission circuit 220 may invert a portion of data loaded on first data transmission lines to fourth data transmission lines TIOIORL, TIOFOFL, TIOIORH, and TIOFOFH and transfer the inverted data to fifth data transmission line MIOR and 6th data transmission line MIOF. For example, second transmission circuit 220 may invert a portion of data loaded on third data transmission lines to fourth data transmission lines TIOIORH and TIOFOFH (e.g. for example). 6 'And 7'). The third Transmission circuit 230 can transmit data of fifth data transmission line MIOR and data 6th data transmission line MIOF to 2:1 serial conversion in @timetimewith, and then transmit the result to data node DQ. 5 Shows : Because at least one of first transmission circuits through third transmission circuits 210,220 and 230 inverts a portion of the data transferred by the circuit, the data patterns 210 data transmission line to 220 data transmission line TIOIORL, TIOFOFL, MIOR and MIOF are compared to first 1st 4 data transmission lines TIOIORL, TIOFOFL, TIOIOLs shown in 6th FIG. 6th, respectively. TIOFOFH, MIOR and MIOF data patterns are more diverse. Thus, the write operation test of the base die 114 can be performed more efficiently. Although FIG. 5 shows first transmission circuits of third transmission circuits to 210,220 transmission circuits 230 and first transmission circuits 210 and second invert a portion of data, only one of 220 transmission circuits through first transmission circuits third and 210,220 inverts or 230 transfers a portion of data to first transmission circuit third 210, respectively. 220 And 230 all invert a portion of the data. 6 Is a block diagram illustrating first transmission circuits (e.g. 2 transmission circuit first of FIG. 210) according to one embodiment of the present invention. 6 Depicts 5 transmission circuits first that operate the same as first of FIG. 210 operating. The first Transmission circuit 210 may transmit data of first coupler TSVSVR to 8th data transmission line TIOIORL in synchronization with first strobe signals RDQDQDQS0 to second strobe signals RDQDQDQS7 and the data of first couplers TSVSVF to fourth data transmission lines TIORL, respectively. TIOFOFL, TIOIORH, and TIOFOFH. The first Transmission circuit 210 may transmit data synchronized with four strobe signals RDQDQDQS0, RDQDQS1, RDQDQDQS6 and RDQDQDQS7, but it may be to be adjacent to the four strobe signals RDQDQS2, respectively. The data synchronized with RDQDQDQS3, RDQDQDQS4 and RDQDQDQS5 are inverted and transmitted. In short, first transmission circuit 210 may transmit four data among the eight data transmitted by itself as it is, and invert and transmit the other four data thereto. The first Strobe signals RDQDQDQS0 to 8th strobe signals RDQDQDQS7 can be generated by dividing the data strobe signal RDQS used in the read operation, and the activation periods first strobe signals RDQDQDQS0 to 8th strobe signals RDQDQDQS7 do not overlap each other. To FIG. 7, the data strobe signal RDQS DQS DQS DQS and the first strobe signal RDQDQDQS0 to 8th strobe signals RDQDQDQS7 can be understood. To FIG. 6, first transmission circuit 210 may include first transmission units 610 through 8th transmission units 680, first latches 690 through fourth latches 720 and first drivers 730 through fourth driver 760. The first Transmission unit 610 may invert the data first coupler TSVSVR in response to first strobe signal RDQDQDQ0 and transmit the inverted data to first latch 690. The three-phase inverter 611 may be turned on when first strobe signal RDQDQDQS0 is deactivated to a logic low level, for. When first strobe signal RDQDQDQS0 is activated to a logic high level, three-phase inverter 611 can be turned off, latch 612 is activated and three-phase inverter 613 can be activated. Through these operations, the operation is completed. Data synchronized with first strobe signal RDQDQDQS0 may be inverted and transmitted to first latch 690. The second Transmission unit 620 may invert the data second coupler TSVSVF in response to second strobe signal RDQDQS1 and transmit the inverted data to second latch 700. The three-phase inverter 621 may be turned on when second strobe signal RDQDQ0 is deactivated to a logic low level, for. When second strobe signal RDQDQ0 is activated to a logic high level, three-phase inverter 621 can be turned off, latch 622 can be activated and three-phase inverter 623 can be activated. Through the operations, data synchronized with second strobe signals RDQDQS1 may be inverted and transmitted to second latches 700. The third Transmission unit 630 may transmit the data third coupler TSVSVR to first latch third in response to 710 strobe signal RDQDQS2. The transfer gate 631 may be turned on when third strobe signal RDQDQS2 is deactivated to a logic low level, for. When third strobe signal RDQDQS2 is activated to a logic high level, transmission gate 631 may be turned off, latch 632 may be activated and three-phase inverter 633 may be activated. Through the operations, data synchronized with third strobe signals RDQDQS2 may be transmitted to third latches 710. The fourth Transmission unit 640 may transmit data fourth coupler TSVSVF to second latch fourth in response to 720 strobe signal RDQDQDQS3. The transfer gate 641 may be turned on when fourth strobe signal RDQDQDQS3 is deactivated to a logic low level. When fourth strobe signal RDQDQDQS3 is activated to a logic high level, transmission gate 641 may be turned off, latch 642 may be activated and three-phase inverter 643 may be activated. Through the operations, data synchronized with fourth strobe signals RDQDQDQS3 can be transmitted to fourth latches 720. The fifth Transmission unit 650 may transmit data fifth coupler TSVSVR to first latch first in response to 690 strobe signal RDQDQDQS4. The transfer gate 651 may be turned on when fifth strobe signal RDQDQDQS4 is deactivated to a logic low level. When fifth strobe signal RDQDQDQS4 is activated to a logic high level, transmission gate 651 may be turned off, latch 652 may be activated and three-phase inverter 653 may be activated. Through the operations, data synchronized with fifth strobe signals RDQDQDQS4 can be transmitted to first latches 690. 6th Transmission unit 660 may transmit data 6th coupler TSVSVF to second latch second in response to 700 strobe signal RDQDQDQS5. The transfer gate 661 may be turned on when 6th strobe signal RDQDQDQS5 is deactivated to a logic low level. When 6th strobe signal RDQDQDQS5 is activated to a logic high level, transmission gate 661 may be turned off, latch 662 may be activated and three-phase inverter 663 may be activated. Through the operations, data synchronized with 6th strobe signals RDQDQDQS5 can be transmitted to second latches 700. 7th Transmission unit 670 may transmit data 7th coupler TSVSVR to first latch third in response to 710 strobe signal RDQDQDQS6. The three-phase inverter 671 may be turned on when 7th strobe signal RDQDQDQS6 is deactivated to a logic low level, for. When 7th strobe signal RDQDQDQS6 is activated to a logic high level, three-phase inverter 671 can be turned off, latch 672 can be activated and three-phase inverter 673 can be activated. By the operations, data synchronized with 7th strobe signals RDQDQDQS6 can be inverted and transmitted to third latches 710. 8th Transmission unit 680 may transmit data 8th coupler TSVSVF to second latch fourth in response to 720 strobe signal RDQDQDQS7. The three-phase inverter 681 may be turned on when 8th strobe signal RDQDQDQS7 is deactivated to a logic low level, for. When 8th strobe signal RDQDQDQS7 is activated to a logic high level, three-phase inverter 681 can be turned off, latch 682 can be activated and three-phase inverter 683 can be activated. By the operations, data synchronized with 8th strobe signals RDQDQDQS7 can be inverted and transmitted to fourth latches 720. The first Latch 690 may latch the data transferred from first transmission units 610 and fifth transmission unit 650 and invert it to be inverted, for example. And the inverted data is transferred to first driver 730. The first Driver 730 may drive data received from first latch 690 to first data transmission line TIOIORL. The read enable signal RDEDEN may be a signal that is activated in a read operation. The first Driver 730 may be activated during a read operation, where in a read operation, a write operation is performed, for example. The read enable signal RDEDEN is activated to a logic high level and the read enable signal RDEDENB is activated to a logic low level. The second Latch 700 may latch the data transferred from second transmission units 620 and 6th transmission unit 660 and invert it to be inverted, for example. And the inverted data is transferred to second driver 740. The second Driver 740 may drive data received from second latch 700 to second data transmission line TIOFOFL. The read enable signal RDEDEN may be a signal that is activated in a read operation. The second Driver 740 may be activated during a read operation, where in a read operation, a write operation is performed, for example. The read enable signal RDEDEN is activated to a logic high level and the read enable signal RDEDENB is activated to a logic low level. The third Latch 710 may latch the data transferred from third transmission units 630 and 7th transmission unit 670 and invert it to be inverted, for example. And the inverted data is transferred to third driver 750. The third Driver 750 may drive data received from third latch 710 to third data transmission line TIOIOs. The read enable signal RDEDEN may be a signal that is activated in a read operation. The third Driver 750 may be activated during a read operation, where in a read operation, a write operation is performed, for example. The read enable signal RDEDEN is activated to a logic high level and the read enable signal RDEDENB is activated to a logic low level. The fourth Latch 720 may latch the data transferred from fourth transmission units 640 and 8th transmission unit 680 and invert it to be inverted, for example. And the inverted data is transferred to fourth driver 760. The fourth Driver 760 may drive data received from fourth latch 720 to fourth data transmission line TIOFOFH. The read enable signal RDEDEN may be a signal that is activated in a read operation. The fourth Driver 760 may be activated during a read operation, where in a read operation, a write operation is performed, for example. The read enable signal RDEDEN is activated to a logic high level and the read enable signal RDEDENB is activated to a logic low level. 8 Is a block diagram illustrating second transmission circuits (e.g. 2 transmission circuit second of FIG. 220) according to one embodiment of the present invention. In FIG. 8, 5 transmission circuits second which operate as shown 220, are depicted in the. The second Transmission circuit 220 may synchronize first data transmission lines to 8th data transmission lines TIOIOLs in synchronization with first strobe signals RDQDQDQS0 to fourth strobe signals RDQDQDQS7. Data TIOFOFL, TIOIORH, and TIOFOFs are output to fifth data transmission line MIOR and 6th data transmission line MIOF. The second Transmission circuit 220 may transmit data synchronized with four strobe signals RDQDQDQS0, RDQDQS1, RDQDQDQS6 and RDQDQDQS7, but they may be to other four strobe signals RDQDQS2, respectively. The data synchronized with RDQDQDQS3, RDQDQDQS4 and RDQDQDQS5 are inverted and transmitted. In short, second transmission circuit 220 can transmit four data among the eight data transmitted by second transmission circuit 220 as it is, and invert and transmit the other four data thereto. To FIG. 8, second transmission circuit 220 may include 9th transmission units 810 through sixteenth transmission units 880, fifth latches 890 through 6th latches 900 and fifth drivers 910 through 6th driver 920. 9th Transmission unit 810 may invert the data first data transmission line TIOIORL in response to first strobe signal RDQDQDQ0 and transmit the inverted data to fifth latch 890. The transfer gate 812 may be turned on when first strobe signal RDQDQDQS0 is activated to a logic high level, and data first data transmission line TIOIORL may be transmitted to 811 latch 812 through inverter fifth and transfer gate 890. 10th Transmission unit 820 may invert the data second data transmission line TIOFOFL in response to second strobe signals RDQDQS1 and transfer the inverted data to 6th latches 900. The transfer gate 822 may be turned on when second strobe signal RDQDQ0 is activated to a logic high level, and data second data transmission line TIOFOFL may be transmitted to 821 latch 822 through inverter 6th and transfer gate 900. The eleventh transmission unit 830 may transmit, in response to third strobe signals RDQDQS2, data third data transmission line TIOIOHs to fifth latches 890. The three-phase inverter 832 may be turned on when third strobe signal RDQDQS2 is activated to a logic high level, and data third data transmission line TIOIORH may be transferred to 831 latch 832 through inverter fifth and three-phase inverter 890. The twelfth transmission unit 840 may transmit the data fourth data transmission line TIOFOFH to fourth latches 6th in response to 900 strobe signals RDQDQDQS3. The three-phase inverter 842 may be turned on when fourth strobe signal RDQDQDQS3 is activated to a logic high level, and data fourth data transmission line TIOFOFH can be transmitted to 841 latches 842 through inverter 6th and three-phase inverter 900. The thirteenth transmission unit 850 may transmit the data fifth data transmission line TIOIORL to first latches fifth in response to 890 strobe signals RDQDQDQS4. The three-phase inverter 852 may be turned on when fifth strobe signal RDQDQDQS4 is activated to a logic high level, and data first data transmission line TIOIORL can be transferred to 851 latch 852 through inverter fifth and three-phase inverter 890. The fourteenth transmission unit 860 may transmit, in response to 6th strobe signal RDQDQDQS5, data second data transmission line TIOFOFs to 6th latches 900. The three-phase inverter 862 may be turned on when 6th strobe signal RDQDQDQS5 is activated to a logic high level, and data second data transmission line TIOFOFL may be transferred to 861 latches 862 through inverter 6th and three-phase inverter 900. The fifteenth transmitting unit 870 may transmit data 7th data transmission line TIOIORH to third latches fifth in response to 890 strobe signals RDQDQDQS6. The transfer gate 872 may be turned on when 7th strobe signal RDQDQDQS6 is activated to a logic high level, and data third data transmission line TIOIORH may be transmitted to 871 latch 872 through inverter fifth and transfer gate 890. The sixteenth transmission unit 880 may invert the data 8th data transmission line TIOFOFH in response to fourth strobe signals RDQDQDQS7 and transmit the inverted data to 6th latches 900. The transfer gate 882 may be turned on when 8th strobe signal RDQDQDQS7 is activated to a logic high level, and data fourth data transmission line TIOFOFH can be transmitted to 881 latch 882 through inverter 6th and transfer gate 900. The fifth Latch 890 may latch the slave 9th transmission unit 810, for example. The eleventh transmission unit 830, the thirteenth transmission unit 850, and the fifteenth transmission unit 870 transmit and invert the data, and transmit the inverted data to fifth the drive 910. The fifth Driver 910 may drive data received from fifth latch 890 to fifth data transmission line MIOR. The read enable signal RDEDEN may be a signal that is activated in a read operation. The fifth Driver 910 may be activated during a read operation, for example. In the read operation, the read enable signal RDEDEN is activated to a logic high level and the read enable signal RDEDENB is activated to a logic low level. 6th Latch 900 may latch the slave 10th transmission unit 820, for example. The twelfth transmission unit 840, the fourteenth transmission unit 860, and the sixteenth transmission unit 880 transmit the same data and invert them, and transmit the inverted data to 6th the drive 920. 6th Driver 920 may drive data received from 6th latch 900 to 6th data transmission line MIOF. The read enable signal RDEDEN may be a signal that is activated in a read operation. 6th Driver 920 may be activated during a read operation, for example. In the read operation, the read enable signal RDEDEN is activated to a logic high level and the read enable signal RDEDENB is activated to a logic low level. To the embodiment, the integrated circuit chip can be effectively tested. Although the present invention has been described with respect to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the present invention as defined by the appended claims.
