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    基于扫描探针显微镜的触觉交互接口的实现方法

    KR2003082144B2
    发明人
    董再励, 刘连庆, 田孝军, 焦念东, 王越超
    受让人
    董再励
    申请人
    中国医学科学院整形外科医院
    申请号
    018184
    申请日
    1989-06-30
    公开(公告)号
    KR2003082144B2
    公开(公告)日
    2018-09-20
    IPC分类号
    H04Q007/34H04Q007/38
    CPC分类号
    -
    优先权号
    39723689
    优先权日
    1989-08-22
    摘要

    Translator circuit comprises a decode section connected to an inverter circuit (BUFF) through an input node (node 5) to couple a selection signal to it. The wordline to be driven (node 1) is connected to ground (VXGND) through a first N-MOS type switch transistor (pull-down 2) with gate (node 0) driven by a selection logic signal applied through the NOR-gate, and connected to the operation voltage (VX) through a second P-MOS type switch transistor (pull-up 3). The first P-MOS type feedback transistor (TP4), has a gate (node 6) directly driven by the wordline. The first feedback transistor is inserted between the operation voltage (VX) and the gate region (node 6) of the second switch transistor (pull-up 3). The second N-MOS type feedback transistor (TN3) has a gate directly driven by the wordline (node 18).

    The second feedback transistor is inserted between the connection node (node 6) between first feedback transistor (TP4) and the gate of the second switch transistor (pull-up 3) and the input node (node 0) on the gate of the first switch transistor (pull-down 2). The connection node (node 6) between the first feedback transistor (TP4) and the gate of the second switch transistor (pull-up 3) is connected to ground through a decoupling transistor (TN1) of N-MOS type. The decoupling transistor gate is driven by selection signal once inverted and received from the connection node (node 5) between the inverter (BUFF) and NOR-gate circuits.

    ADVANTAGE -Provides suitable circuit adapted to supply voltages fully variable within acceptable range and adapted to operate in very fast manner.

    权利要求
    1 . A system comprising: one or more processors; and one or more computer-readable media storing instructions that, when executed by the one or more processors, perform operations comprising: determining a junction in an environment based at least in part on map data, the junction comprising a first lane and a second lane; determining that an autonomous vehicle is located in the first lane; determining a first exit point associated with the second lane of the junction based at least in part on the map data; determining a first trajectory for the autonomous vehicle to follow through the junction from the first lane into the second lane and passing through the first exit point; detecting, based at least in part on sensor data, an object located in the second lane; determining an overlap area comprising a first area of a possible overlap between the autonomous vehicle and the object and based at least in part on a second area associated with the first trajectory; determining, based at least in part on detecting the object, a merge location at which a path of the first lane and a path of the second lane merge; determining a second exit point associated with the overlap area based at least in part on the merge location; determining a second trajectory for the autonomous vehicle based at least in part on the second exit point; and controlling the autonomous vehicle to follow the second trajectory.
    2 . The system of claim 1 , wherein the second exit point for the overlap area reduces a size of the overlap area from the first exit point of the overlap area.
    3 . The system of claim 1 , wherein the second exit point for the overlap area is further based on a safety distance added to the merge location.
    4 . The system of claim 3 , wherein the safety distance is based at least in part on one or more of a speed limit associated with the second lane or a trajectory of the object.
    5 . A method comprising: determining a junction in an environment, the junction comprising a first lane and a second lane; detecting an object located in the second lane; determining, responsive to detecting the object, a merge location at which a first path of the first lane and a second path of the second lane merge; determining an exit point for an overlap area associated with a vehicle and the object based at least in part on the merge location; determining a trajectory for the vehicle to enter the second lane based at least in part on the exit point; and controlling the vehicle to follow the trajectory.
    6 . The method of claim 5 , wherein the trajectory is a first trajectory and the vehicle enters the second lane prior to the object entering the overlap area, the method further comprising: detecting that the object enters a threshold distance of the vehicle in the overlap area; and determining a second trajectory for the object, the second trajectory responsive to the object entering the threshold distance and based at least in part on a prediction that the object will follow the vehicle in the second lane, wherein controlling the vehicle to follow the trajectory comprises preventing the vehicle from yielding to the object based at least in part on the second trajectory for the object.
    7 . The method of claim 5 , wherein the trajectory for the vehicle to enter the second lane comprises a turn action or a merge action.
    8 . The method of claim 5 , wherein the first path substantially follows a first center line of the first lane and the second path substantially follows a second center line of the second lane.
    9 . The method of claim 5 , further comprising: determining a size of the junction from map data; and determining first dimensions of the overlap area based at least in part on the size of the junction, wherein determining the exit point for the overlap area comprises determining second dimensions of the overlap area, the second dimensions being smaller than the first dimensions.
    10 . The method of claim 5 , wherein determining the exit point for the overlap area is further based on a safety distance added to the merge location.
    11 . The method of claim 10 , wherein the safety distance is based at least in part on a speed limit associated with the second lane or a trajectory of the object.
    12 . The method of claim 11 , wherein the safety distance is further based on a time for the vehicle to reach the speed limit from a current speed.
    13 . One or more computer-readable media storing instructions that, when executed by one or more processors, perform operations comprising: determining a junction in an environment, the junction comprising a first lane and a second lane; determining a vehicle trajectory for a vehicle to enter the second lane from the first lane and into the second lane; detecting an object located in the second lane; determining an object trajectory associated with the object; determining a merge location at which a first path of the first lane and a second path of the second lane merge; determining an overlap area between an area associated with the vehicle trajectory and the object trajectory; determining an exit point for the overlap area based at least in part on the merge location; altering, as an adjusted vehicle trajectory and based at least in part on the exit point, the vehicle trajectory; and controlling the vehicle to follow the adjusted vehicle trajectory.
    14 . The one or more computer-readable media of claim 13 , wherein the operations further comprise: detecting that the object enters a threshold distance of the vehicle in the overlap area; and determining a second object trajectory for the object responsive to the object entering the threshold distance and based at least in part on a prediction that the object will follow the vehicle in the second lane, wherein controlling the vehicle to follow the adjusted vehicle trajectory comprises preventing the vehicle from yielding to the object based at least in part on the second object trajectory for the object.
    15 . The one or more computer-readable media of claim 13 , wherein the vehicle trajectory for the vehicle to enter the second lane comprises a turn action or a merge action.
    16 . The one or more computer-readable media of claim 13 , wherein the first path substantially follows a first center line of the first lane and the second path substantially follows a second center line of the second lane.
    17 . The one or more computer-readable media of claim 13 , the operations further comprising: determining a size of the junction from map data; and determining first dimensions of the overlap area based at least in part on the size of the junction, wherein determining the exit point for the overlap area comprises determining second dimensions of the overlap area, the second dimensions being smaller than the first dimensions.
    18 . The one or more computer-readable media of claim 13 , wherein determining the exit point for the overlap area is further based on a safety distance added to the merge location.
    19 . The one or more computer-readable media of claim 18 , wherein the safety distance is based at least in part on a speed limit associated with the second lane.
    20 . The one or more computer-readable media of claim 19 , wherein the safety distance is further based on a time for the vehicle to reach the speed limit from a current speed.
    说明书
    [0001]CROSS-REFERENCE TO RELATED APPLICATIONS
    [0002]Provisional Application 63305270, filed on Feb. 1, 2022. This current non-provisional application has no material changed from the said previously filed provisional.
    [0003]FIELD OF INVENTION
    [0004]The current invention is applicable to fields of information technology. Specifically, the current invention provides fast and highly reliable methods and apparatuses for digital data error detection and correction, especially in communication channels. The invention can enable high speed highly reliable communication channels to be established even under the challenge of poor physical signal conditions. The invented methods and apparatuses have lower computation complexity thus perform much faster than legacy forward error correction methods. The current invention also allows fast and reliable data storage systems to be built cost effectively. Possible usage fields include long distance and deep space communications, wired and wireless networks, high speed computer data connections, data storage devices and systems, distributed data storage.
    [0005]RELATED PRIOR ARTS
    [0006]The volume of various digital data in our technology world today is astronomical and grows exponentially every year. Data is processed, transferred and stored. Data storage and communication is a critical part of our technology world today. Data integrity must be protected during communication so that even though a part of the data is received damaged, the error can be detected and fixed so the full and correct data will be received. This protection can be done by inserting extra bits or blocks of data containing redundant information, the receiving end can then use the extra data to check for errors and fix them, using computation methods called forward error correction, or FEC. There are two categories of such data error recovery. The first is called forward error correction, which deals with individual bit errors that are detected but the exact location of the error bits are unknown. Once the precise error bits are determined, the error bits are simply fixed by flipped them between 1 and 0. The second category of error recovery is called forward erasure correction. It deals with erroneous blocks of data. We know location of the error data blocks, but do not know the exact pattern of bit errors, so the error data blocks are assumed to be lost or erased. The erased blocks can be computed from the extra data containing needed repair information.
    [0007]In typical communication channels, forward error corrections are first applied to data received to fix most bit, and checksum blocks are attached to data packets for integrity check. If a mismatched checksum is found, the data packet has errors and so is erased. But it can still be recovered from extra data packets using forward erasure correction. Combined together, with forward error correction fixing raw bit errors and forward erasure correction repairing erased or dropped data packets, any communication channel can deliver digital data highly reliably.
    [0008]FEC algorithms have a long history of development since the invention of Hamming Codes in 1950. Today we have Reed-Solomon Codes, invented in 1960, for both the bit error correction and block erasure correction. We have the Viterbi Codes, BCH Codes, Turbo Codes, LDPC (Low Density Parity Check) and Polar Codes for bit level error correction. Researchers even proposed soft decision decoders, using extra information to fix bit errors more accurately.
    [0009]However all the prior art bit error correction algorithms are complex and have high computation cost. Many of them were invented decades ago. The LDPC was invented in 1963 but forgotten for 33 years due to its impractically high computation complexity, until it was rediscovered in 1996. Today LDPC is one of the major bit error correction algorithms used in high speed networks, with no good replacement in sight. Likewise even though there are plenty of researches to adopt Polar Codes, and put it into one of the standard for 5G wireless networks, the high computation cost prevents wide adoption. Expensive high end micro processors were developed just to handle bit error corrections. Very stringent signal quality requirements are imposed to reduce raw bit error rates to acceptable levels for the FEC algorithms to handle.
    [0010]Just to give one example of how much is the complexity of existing FEC algorithms; let us have a look at LDPC. The algorithm partitions the data stream into large frames containing many thousands of data bits, extra parity bits are computed from a small set of pseudo randomly picked data bits, and inserted in the data stream. On the receiving end, if the parity bits do not match the computation, it indicates presence of error bits. Determining which bits might be the error bits is a complicated computation using floating point arithmetic and Bayesian statistics based formulas called belief propagation algorithms. The computation often must be repeated 10s or 20s of iterations in order to fix one error bit. As modern network connections push for 100 or even 400 gigabits per second speed, and more complicated signal modulation schemes with high raw bit error rates, existing FEC algorithms simply cannot work fast enough to be practical.
    [0011]Wireless cellular networks are not the only place requiring bit error corrections. Our inter-continental data traffic goes through ocean-crossing undersea optical fiber cables as light. Light attenuates as it propagates along the fiber. Thus a lot of relay units are needed to boost the signal and fix errors. The high complexity and limited error correction capability of existing FEC algorithms increase the cost and limit the reach and throughput of inter-continental optical fibers.
    [0012]In summary, the industry desperately needs novel FEC methods that computes fast and fix data errors more effectively, to allow development of next generation communication technology in multiple application fields, including deep space communication, satellite relay and satellite to ground communication, aviation and aerospace communication, cellular networks, IoT wireless networks, industry automation and many more networking application fields.
    [0013]SUMMARY OF INVENTION
    [0014]Present invention provides novel methods and apparatuses for very fast and highly accurate data forward error correction, enabling faster and extremely reliable communication channels to be built even under challenging conditions of poor quality of physical signals.
    [0015]Any forward error correction scheme must add extra bits and data packets, called parity bits and parity packets. When data is received, the extra information in the parity bits and parity packets help to determine if there is error in the data received, and if there are errors, where are the error bits, so that the errors can be repaired as much as possible. A new FEC scheme must handle production of the parity bits and parity packets differently, and on the receiving end, interprets the parity information in different ways, to allow faster processing.
    [0016]In examining how FEC algorithms work, we recognize the principle that parity bits and packets only help to identify and fix errors of the data bits or packets that the parity was computed from in the first place. A parity bit or packet contains no information of data bits or packets that it has no dependency on thus can tell us nothing about the unrelated data.
    [0017]Therefore, we find a weakness in LDPC, Low Density Parity Check, and propose the first novelty of the current. In LDPC data is segregated into frames, error bit correction is done within each frame, not beyond current frame. Each data bit is associated with very few parity bits and each parity bit is associated with very few data bits. Thus the name low density parity check. The sparseness of association is necessary to reduce computation complexity. But it also reduces reliability of error correction. When only a very few parity bits can suggest an error in a data bit, it is unclear whether the data bit is wrong, or the parity bits themselves are wrong, or some other associated data bits could be wrong. This leads to a shortcoming in LDPC, called error floor. It's very difficult to reduce residual bit error rate to below a threshold.
    [0018]The first novelty of current invention provides an encoding engine which produces a near infinite sequence of parity useful to identify and fix data errors. Thus we no longer use so called low density parity. Instead we have high density parity check. Each of parity has a good chance to help identify and fix any data bit error that occurs before the parity. So there is an infinite chance to fix any data bit error. The chance of an error remains unfixed approaches 0.
    [0019]The second novelty of the current invention provides fast encoding of parity packets containing multiple parity bits. Individual bits in a parity packet operate in parallel. The parity packets are encoded through an encoding engine using bitwise exclusive or operations. This novelty allows the encoding and decoding operations to operate on one multiple bits packet at a time, instead of one bit at a time, thus the encoding and decoding speed is much faster.
    [0020]The third novelty of current invention provides a pre-processing method to add check bits to blocks of data. The check bits allow locating and fixing of the simplest bit errors thus reduce the raw bit error rate for the practicality of the next steps of processing. The check bits can be interleaved with the data bits, or can be placed together to form a checksum. Each check bit is the exclusive or of a subset of the data bits. If all check bits match it suggests that the data block is likely correct. Mismatched check bits can be used to form an index for fetching a repair entry from a pre-calculated lookup table, calculated based on statistics. If the repair entry is non-zero, it is applied to repair bits in the data block, which likely results in a corrected data block. This pre-processing step is fast and reduces residual bit errors for the next steps.
    [0021]The fourth novelty of current invention is the novel methods we use to narrow down likely locations of errors based on whether any repair packet and any of their bits are zero or not, by accumulating confidence scores. When enough confidence scores are accumulated, data packets are either accepted as correct, or identified error bits are fixed.
    [0022]The fifth novelty of the current invention is the novel methods to recombine repair packets to reduce their dependencies and thus they can more accurately suggest which data packets may contain errors. This makes the error information in repair packets more useful.
    [0023]This summary only provides an outline of the principles of the present invention and lists the main novelties in a non-exhaustive fashion. The details of the invented process methods and apparatus parts, and practical embodiment examples will be illustrated in the next sections.
    [0024]Present invention is a non-provisional application as a follow up to a previously filed provisional application. Specific claims are enumerated in the claims section. The main spirit and novelties of the invention, however, are sufficiently stated in this document and also in previously filed provisional application, with no material change since the provisional filing.
    [0025]BRIEF DESCRIPTION OF DRA WINGS This section is skipped as no figure is furnished in this non-provisional application.
    [0026]DETAILED DESCRIPTION OF INVENTION
    [0027]The present invention provides a plurality of data encoding and error correction processing steps and apparatuses to process input data to produce interleaved parity data and to process such interleaved data and parity data to identify and fix bit errors and to deliver original input data correctly. The present invention is useful in helping to build fast and highly reliable communication networks.
    [0028]As stated in the summary section, there are a few novelties in the current invention:
    [0029]1. Providing an entropy encoding engine which can produce a near infinite sequence of parity, each one has a good chance to be useful to fix any data bit error that occurs before the parity. See claim 1 step 1 c ; Claim 2 step 2 b ; Claim 4 ; Claim 8 unit 8 c ; Claim 9 unit 9 d and claim 10 . 2. Encoding packets of parity bits instead of encoding one parity bit at a time, with individual bits in a parity packet operate in parallel, for fast encoding and decoding throughput speed. See claim 1 step 1 c ; Claim 2 step 2 b ; Claim 4 ; Claim 8 unit 8 c ; Claim 9 unit 9 d and claim 10 . 3. Providing a pre-processing method to add check bits to packets of data, allowing repair of the most frequent bit error patterns, reducing the raw bit error rate for the main decoding steps. See claim 1 step 1 b ; Claim 2 step 2 a ; Claim 9 unit 9 b and 9 c ; and claim 10 . 4. Computing confidence scores of data packets and bits based on whether associated parity packets match or not, and set bits of repair packets calculated, and based on the scores to accept likely correct data packets and repair likely incorrect ones. See claim 2 step 2 d and 2 e , etc. 5. Recombining repair packets to simplify their dependencies on data packets so they can more specifically suggest which packets may be wrong, making the error information more useful. See claim 5 and see further explanations as follows.
    [0030]The details of these novelties and example embodiments will be discussed next.
    [0031]Basic Principles of Current Invention
    [0032]The first novelty of the current invention is that an entropy encoding engine is used which is capable of producing an infinite sequence of parity symbols, after original data symbol information is encoded and persisted in the encoding engine. This contrasts against not just the LDPC, but all other prior art FEC schemes, where each data bit is related to very few parity bits, and each parity bit is related to very few data bits, resulting in limited chance of cross-checking to fix errors reliably. As the invented encoding engine continuous to produce a sequence of parity symbols with good chance of correlated to any data symbols in question, any symbol errors are exposed by subsequent parity symbols repeatedly, until they are eventually fixed. Sec claim 4 and see further explanations to follow.
    [0033]The invented entropy encoding engine stores N data symbols. All symbols have the same size, which can be one or many bits. Bitwise exclusive or operations are used in the engine. It can carry out three types of operations: input a data symbol; update; output a parity symbol. In each of operation iteration, one data input and one update is performed, but output parity symbol is performed only when needed, depending on the desired parity to data ratio. For data symbol input, the input symbol is exclusive or into a subset of the symbols stored in the engine. For the update, symbols are rotated, and some symbols are exclusive or into other symbols. Note that all operations are just a series of atomic exclusive or operations, with one symbol exclusive or unto another symbol, a reversible step. Since the steps are reversible, entropy stored in the engine do not change. This is why the engine can continue indefinitely to emit parity symbols correlated to previous data symbols. Two copies of the same engine operate both on the sender side and on the receiver side. If all data is received without error, the sender and receiver engine will produce matching parity symbols. If the parity symbols do not match, the exclusive or between them, called repair symbols, are non-zero, and they help to identify and fix the errors.
    [0034]In the second novelty of the current invention, multiple bit symbols are used in the above-mentioned entropy engine. For example a symbol can contain 4096 bits or 512 bytes. This allows faster processing, as the engine will process multiple bits instead of just one bit at a time. Sec claim 1 step 1 a and claim 3 . Note a coded symbol block contains both data and parity bits.
    [0035]In the third novelty of the current invention, an extra encoding stage is added to reduce raw bit error rate. The way it works is that raw input data is first processed by above mentioned entropy encoding engine and separated into data symbols with some generated parity symbols mixed in, depending on the parity to data ratio. Then the encoded data pass through a second stage of encoding, which can be a legacy bit error correction scheme like BCH or Reed-Solomon or LDPC, but can also be a novel checksum as provided by the current invention. See claim 3 . For example, a simple 24 bits checksum can be calculated from 128 bits of data. The checksum can detect most errors, and allow the most frequent simple bit errors to be fixed, thus reducing the remaining bit error rate. On the receiver side, the same checksum is computed and compared to see if they match or not. If they mismatch, the exclusive or value between the two checksums is used to index into a lookup table to find simple bit error fixes. After the initial processing, some data errors can remain but the error rate is lower for main decoder to process.
    [0036]In the fourth novelty of the current invention, a receiver computes repair symbols by bitwise exclusive or received parity symbols against the locally generated ones. See claim 2 step 2 b . Since the same encoding engine runs both on the sender side and the receiver side, the two parity symbols should be identical and thus the calculated repair symbols are zero. Whether any repair symbols are zero or not, and if they are not zero, the non-zero bits in the repair symbols provide useful information to determine location of error symbols and error bits. The current invention provides novel method to use this information to find and fix the data errors.
    [0037]In one embodiment example, a numerical confidence score is used to represent the likelihood that a data symbol is likely wrong, and each bit can also have a score of how likely the bit is in error. For example, a logarithm score of 0 means that there is equal possibility there is error or not. A score of 1.0 means there is 21.0, or 2 times likelihood there is error, than there is not. A score of −1.0 means there is 2-1.0, or half likelihood there is error, versus there is not. In other embodiment examples, traditional statistical calculations, called belief propagation, can be carried out to compute the confidence score. See claim 7 and step 7 c.
    [0038]Thus, for example, when a repair symbol is computed to be zero, and it correlates to ten recent data symbols, there is a very high chance that all ten data symbols have no error, with a much lower chance that at least two symbols have error, and their errors happen to cancel out, resulting in a zero repair symbol. So, we lower the score of each data symbols by 8, to account for that there is 2{circumflex over ( )}8=256 times less odd of having errors than not having errors. Likewise, when a repair symbol is non-zero, the non-zero bits in it suggest corresponding bits in correlated data symbols are more likely to be wrong, so the scores of such data bits are raised accordingly.
    [0039]When scores of data bits become significant, these data bits are likely wrong so they are flipped to correct the errors. When a data symbol reaches such a low score there is virtually no chance it still contains error, the symbol is accepted as correct and thus no longer considered for any further processing. And the processing moves forward to subsequent data symbols.
    [0040]After such processing there should be no more non-zero repair symbol, suggesting there are no more detected errors. If there are still detected errors, the data is processed again using the same processing steps, to eradicate any remaining data errors.
    [0041]While the fourth novelty provides good methods to identify and fix data errors based on whether repair symbols are zero or not, and based on correlations between data symbols and repair symbols, it can get difficult trying to pin-point which data symbols may have errors, as more repair symbols are processed, and each repair symbol can correlate to a lot data symbols.
    [0042]The fifth novelty of the current invention solves this problem by providing a method to recombine repair symbols, so that the recombined repair symbols have fewer data symbols correlated to them. See claim 5 and especially step 5 d . The fewer correlations make it easier to locate data errors because the search space is narrowed. This can be achieved by recombining the repair symbols so that for each bit in the repair symbols, no more than one repair symbol has that bit as 1. The same bit in all the other recombined repair symbols should be 0.
    [0043]An example embodiment example takes the following steps to achieve such a result. First we ensure the first data bit in the first repair symbols is set. If not we search in the rest of the repair symbols to see if anyone has that bit set. If we find one, the repair symbol is exclusive or unto the first repair symbol, so now it has its first bit set. If no repair symbol has that bit set, then we skip the first bit and examine the second bit instead. Second, with the first repair symbol carries the first bit as 1, we ensure that the same bit is 0 in all other repair symbols. For anyone having the same bit as 1, we exclusive or the first repair symbol into it to cancel out the set bit.
    [0044]This processing is repeated for all current processing repair symbols. Eventually we have a few non-zero repair symbols correlated to very few data symbols, and a lot more repair symbols with zero value which are correlated to a lot of error free data symbols. This facilitate using the fourth novelty methods to pinpoint and repair data symbols with errors, and using the zero value repair symbols to clear data symbols as likely error-free and need no more processing.
    [0045]There can be a lot of variations in practical embodiments without deviating from the spirit of the five novelties as explained above. All such variations of practical embodiments are considered included and incorporated in the current invention.
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