Fault-tolerant quantum computing requires large-scale superconducting processors, yet monolithic architectures face increasing constraints from wiring density, crosstalk, and fabrication yield. Modular superconducting platforms offer a scalable alternative, but achieving high-fidelity entangling gates between distant modules remains a central challenge, particularly for highly coherent fixed-frequency qubits. Here, we propose a distributed hardware architecture designed to overcome this bottleneck by employing a pair of double-transmon couplers (DTCs). By synchronously controlling the two DTCs stationed at opposite ends of a macroscopic cable, our scheme strongly suppresses residual static inter-module coupling while enabling on-demand activation of a non-local cross-Kerr interaction with an on/off ratio exceeding 10^6. Through comprehensive system-level numerical simulations incorporating realistic hardware parameters, we demonstrate that this mechanism can realize a remote controlled-Z (CZ) gate with a fidelity over 99.99% between fixed-frequency transmons housed in separate packages interconnected by a 25 cm coaxial cable. These results establish a highly viable, hardware-efficient route toward high-performance distributed superconducting processors.

Leakage to noncomputational states limits the speed of single-qubit gates in weakly anharmonic transmons. Conventional pulse-shaping methods, including derivative removal by adiabatic gate (DRAG), primarily suppress the leakage remaining at the end of a gate. Here we demonstrate that endpoint leakage and the transient leakage population that accumulates during the gate represent distinct control objectives. Endpoint leakage is associated with the drive spectrum at the anharmonicity, whereas transient exposure depends on spectral weight over a finite frequency band and governs the additional leakage induced by dephasing. A spectral null at the leakage transition therefore suppresses the endpoint amplitude without necessarily reducing transient exposure. Based on this distinction, we introduce a path–endpoint separation pulse that combines transient-path shaping with a two-tone endpoint correction. For a 10 ns R_X(π/2) gate with an anharmonicity magnitude of 0.2 GHz, numerical simulations show a 21% reduction in transient exposure relative to cosine DRAG and a corresponding 20% reduction in dephasing-induced excess leakage. The two correction tones further suppress residual leakage through the |2⟩ and |3⟩ channels, lowering the coherent endpoint leakage from approximately 7×10^-7 to 3×10^-8 without increasing transient exposure. These results establish transient exposure and endpoint leakage as complementary targets for the design of fast transmon gates.

Capacitors are crucial components of superconducting qubits. Using the energy participation ratio method, we show that arc-edged capacitors reduce interface energy participation and improve electric field distribution relative to rectangular designs, supporting enhanced decoherence time. Here, we further optimize double-pad capacitor geometries by exploring how arc number and profile on opposing sides affect the Purcell-limited upper bound of T_1,limit . We deploy a deep reinforcement learning dual neural network model to enable autonomous, human-in-the-loop-free capacitor shape evolution. With T_1,limit as the optimization target and a fixed 430 μ m× 300 μ m footprint, our optimized arc-edge design exhibits a notable enhancement in the Purcell-limited T_1,limit relative to traditional rectangular capacitors. Subsequent supplementary 3D simulations further reveal that the optimized structure also mitigates surface dielectric loss, suggesting potential improvements in comprehensive coherence performance. This work thus presents a promising simulation-driven approach to the optimized design of superconducting qubit capacitors, with additional coherence benefits supported by complementary dielectric loss analysis.

Electronic Design Automation (EDA) plays a crucial role in classical chip design and significantly influences the development of quantum chip design. However, traditional EDA tools cannot be directly applied to quantum chip design due to vast differences compared to the classical realm. Several EDA products tailored for quantum chip design currently exist, yet they only cover partial stages of the quantum chip design process instead of offering a fully comprehensive solution. Additionally, they often encounter issues such as limited automation, steep learning curves, challenges in integrating with actual fabrication processes, and difficulties in expanding functionality. To address these issues, we developed a full-stack EDA tool specifically for quantum chip design, called EDA-Q. The design workflow incorporates functionalities present in existing quantum EDA tools while supplementing critical design stages such as device mapping and fabrication process mapping, which users expect. EDA-Q utilizes a unique architecture to achieve exceptional scalability and flexibility. The integrated design mode guarantees algorithm compatibility with different chip components, while employing a specialized interactive processing mode to offer users a straightforward and adaptable command interface. Application examples demonstrate that EDA-Q significantly reduces chip design cycles, enhances automation levels, and decreases the time required for manual intervention. Multiple rounds of testing on the designed chip have validated the effectiveness of EDA-Q in practical applications.

Practical quantum advantage hinges on executing deep quantum circuits within the coherence limits of noisy intermediate-scale quantum processors. The absence of native, high-fidelity multi-qubit gates remains a major bottleneck, as their decomposition into single- and two-qubit gates leads to prohibitive depth and error overhead. Here, we propose a hardware-efficient protocol that directly implements a native controlled-controlled-Z (CCZ) gate in a tunable-coupler superconducting circuit. Our theoretical protocol activates a resonant three-qubit interaction via a time-frequency correlated virtual process, explicitly relying on the dynamic resonant exchange within the |101⟩↔ |020⟩ transition manifold. This approach is compatible with standard tunable-coupler architectures without requiring additional control resources. Through a systematic calibration workflow combining pulse shaping and active cancellation of residual phases, we demonstrate a gate fidelity exceeding 99% within 165 ns – significantly outperforming decomposed sequences. Comprehensive error budgeting confirms that the gate performance remains robust against realistic experimental imperfections. Furthermore, we show that this scheme can be naturally extended to a continuous CCPhase(θ) gate set. This work provides a direct, high-fidelity route to three-qubit entanglement, offering promising prospects for efficient execution of quantum algorithms on near-term superconducting hardware.

In superconducting quantum circuits, decoherence errors in qubits constitute a critical factor limiting quantum gate performance. To mitigate decoherence-induced gate infidelity, rapid implementation of quantum gates is essential. Here we propose a scheme for rapid controlled-Z (CZ) gate implementation through energy-level engineering, which leverages Rabi oscillations between the X11) state and the noncomputational state in a tunable-coupler architecture. Numerical simulations achieved a 22-ns nonadiabatic CZ gate with fidelity greater than 99.99%. We further investigated the performance of the CZ gate in the presence of anharmonicity offsets. The results demonstrate that a high-fidelity CZ gate with an error rate below 10-4 remains achievable even with finite anharmonicity variations. Furthermore, the detrimental impact of spectator qubits in different quantum states on the fidelity of the CZ gate is effectively suppressed by incorporating a tunable coupler. This scheme exhibits potential for extending the circuit execution depth constrained by coherence time limitations.

Suppressing critical current density (Jc) fluctuations in Josephson junctions is essential for improving the reproducibility and scalability of superconducting quantum processors. Despite many elucidations of microscopic mechanisms, the physical modulation of Jc by atomic-scale disorder at the metal-insulator interface remains elusive. Here, we reveal that interfacial bonding topology distortions are the dominant source that regulates Jc uniformity. We identify a new disorder metric, Interface Bonding Topology Factor (IBTF), that captures bond-angle fluctuations and oxygen-coordination heterogeneity within Jc variations. Through multivariate analysis, Jc is exponentially correlated with interface disorder and barrier thickness (d) by Jc ∝ e−IBTF⋅d, explaining 91.88% of the observed Jc inhomogeneity. We establish IBTF as a tunable physical degree of freedom whose suppression efficacy enhances significantly with increasing d, and demonstrate its active modulation by twin boundary engineering in electrodes. This work provides a device-oriented strategy and a tunable physical metric beyond single-feature control for scalable high-performance quantum processors.

As quantum computing continues to scale, quantum measurement and control (QMC) are increasingly constrained by calibration workflow complexity and by requirements for low-latency execution, robust exception handling, and traceable workflow governance. Existing frameworks for QMC are specialized and task-specific, while language-model-based agents for QMC suffer from excessive latency and cannot satisfy the strict timing and control-density demands of large-scale quantum systems. Here we propose QMClaw, a general, workflow-oriented framework for QMC built, featuring a local-first, tool-governed, robust architecture. At its core is a RuleEngine-centered control layer that processes structured context, performs rule-based state transitions, and generates execution plans for typical calibration workflows. Language models are used only for natural-language interaction, high-level task understanding, and exception support, keeping the critical fast path efficient. We implement a single qubit tune-up workflow as a demonstration and validation using real quantum device dataset. We also prove that the framework achieves quantitatively acceptable levels in terms of resource cost, LLM calling times and decision latency, enabling its practical deployment in large-scale quantum qubit measurement and control scenarios. This work presents a general workflow-oriented framework for QMC and provides evidence that rule-centered architectures are a promising design choice for scalable quantum-system calibration.

Scaling superconducting quantum processors toward fault-tolerant operation fundamentally necessitates architectures that transcend the practical limits of monolithic chips. Modular processors connected by low-loss superconducting links offer a promising route. However, implementing high-fidelity entangling gates between remote fixed-frequency qubits remains a central challenge. Here, we propose a distributed architecture in which a pair of synchronously modulated double-transmon couplers mediates the interaction between two fixed-frequency transmons housed in separate packages and linked by a macroscopic 25-cm coaxial cable. This scheme enables the on-demand activation of a tunable nonlocal ZZ interaction while strongly suppressing residual static coupling, allowing the superconducting link to function as a gate-native interconnect rather than merely a state-transfer channel. This paradigm achieves an exceptional on/off ratio exceeding 10 6 while strictly preserving intrinsic qubit coherence. Circuit-level numerical simulations under experimentally realistic parameters demonstrate a remote controlled-Z gate fidelity of 99.99%, effectively rendering the macroscopic module boundaries computationally invisible. This hardware-efficient framework offers a promising route beyond the practical limits of monolithic scaling and provides a foundation for distributed quantum error-correction networks.

Quantum cloud platforms are poised to deliver powerful computing capabilities, but users have no direct means to verify which physical device executes their workload. This lack of transparency enables hardware substitution attacks, where a malicious adversary could redirect a job to a substituted or inferior processor. We present a general authentication framework that addresses this problem by constructing multi-dimensional quantum fingerprints from raw measurement data. Without any curve fitting, we directly concatenate the raw statistics of complementary experiments into a high-dimensional feature vector that preserves subtle device-specific information. A Mahalanobis nearest-neighbor classifier achieves 100% benign authentication accuracy on three superconducting processors over a three-week chronological split. The classifier naturally yields an authentication confidence C_claimed which reveals device-specific safety margins and motivates per-device alert thresholds. We assess the framework's robustness under two distinct scenarios. Under additive isotropic Gaussian noise, C_claimed decays predictably at a rate explained by inverse covariance traces, enabling an early warning mechanism. Against white-box adversarial perturbations, the same confidence threshold detects L_2 targeted attacks with near-perfect success and reveals device-dependent empirical thresholds for L_∞ attacks, while untargeted and sparse attacks are ineffective. The proposed framework thus unifies fingerprint extraction, drift-resilient authentication, proactive health monitoring, and adversarial defense, offering a practical step toward trustworthy quantum cloud computing.

High-fidelity quantum interconnection remains a critical challenge for scaling up superconducting quantum chips. Here, we realize a simple fixed coupling scheme to achieve high-fidelity two-qubit gate operation across separate superconducting quantum chips. In this scheme, qubit-qubit coupling between separate chips can be realized via exchange interaction mediated by a bus resonator. By merely tuning the frequency of a single qubit, the resonant mode of the bus resonator can be modulated, enabling high-quality and stable quantum interconnection across different chips. Consequently, the experimentally implemented two-qubit gate operations between separate chips exhibit excellent performance, with a maximum two-qubit CZ gate fidelity reaching 99.57

Limited by the decoherence of qubits as well as the errors of quantum gates, near-term superconducting quantum computers can only run low-depth quantum circuits to achieve acceptable fidelity. One possible way to overcome these limitations is to construct quantum circuits with additional high-fidelity expressive multi-qubit gates. Recently, a new three-qubit gate, denoted as Controlled-CPHASE-SWAP (CCZS), has been implemented through simultaneous Controlled-Z (CZ) gates. The CCZS gate takes less time than a single CZ gate and can be implemented at the coherence limit. However, how to use the CCZS gate in quantum circuit synthesis remains unexplored. In this paper, we construct the quantum fan-out/parity gates, the controlled-phase gate and the locally fully connected CZ gates with the CCZS gate, respectively. Furthermore, applications of the CCZS gate in quantum error correction, quantum Fourier transform and quantum approximate optimization algorithm are also proposed. We evaluate the performance of the CCZS gate in quantum circuit synthesis through simulation and explore its potential advantages over CZ gates.

Currently, variational quantum classification algorithms (VQCAs) generally rely on traditional optimization techniques such as Powell and SLSQP in the parameter optimization session. However, the performance of these methods shows limitations in practical applications. Although the parameter-shift rule can efficiently compute the parameter gradient with quantum circuits, it needs to run the quantum circuit twice repeatedly, which significantly reduces the computation efficiency. In order to overcome this challenge, this paper innovatively integrates the principle of unitary operation in quantum mechanics with the technical characteristics of superconducting quantum chips and elaborately designs some new parameterized quantum gates (PQGs). These PQGs strictly follow the rules of unitary operation, which ensures the stability and accuracy of quantum state evolution while realizing an efficient solution to the parameter gradient. Especially for the gradient calculation of a single qubit and single-angle PQGs, the new method can be completed with only a single quantum circuit run, which greatly improves the computation efficiency. Experimental validation on benchmark datasets such as breast cancer and iris shows that the method proposed in this paper exhibits excellent performance on quantum classification tasks. Compared with the parameter-shift rule, the computation efficiency of the new method is improved by 40%. And the classification accuracy, precision, and other key performance metrics are improved by an average of 5% in comparison with traditional optimization algorithms. This work not only enriches the methodology of quantum machine learning theoretically but also demonstrates its remarkable superiority in practical applications, which indicates that the method has great potential in scientific research and industrial applications.

As the scale of quantum bits expands,manual calibration of quantum bits becomes costly and inefficient.Therefore,the automation of quantum measurement and control is imperative.A frame-work for automated quantum measurement and control is constructed in this work,including 3 modules such as measurement and control experiment,data processing and decision judgment,and 4 databases such as measurement and control experiment library,data processing function library,measurement and control experience library and measurement and control database.The automated calibration of single-qubit properties is completed based on this framework.The calibration of readout gates and single-qubit gates for 24 quantum bits is accomplished in a total of 2.7 h,averaging 6.75 min per qubit.An average single-qubit gate fidelity of 99.28%and a readout fidelity of 78.6%is achieved.

Quantum circuit fidelity is a crucial metric for assessing the accuracy of quantum computation results and indicating the precision of quantum algorithm execution. The primary methods for assessing quantum circuit fidelity include direct fidelity estimation and mirror circuit fidelity estimation. The former is challenging to implement in practice, while the latter requires substantial classical computational resources and numerous experimental runs. In this paper, we propose a fidelity estimation method based on Layer Interleaved Randomized Benchmarking, which decomposes a complex quantum circuit into multiple sublayers. By independently evaluating the fidelity of each layer, one can comprehensively assess the performance of the entire quantum circuit. This layered evaluation strategy not only enhances accuracy but also effectively identifies and analyzes errors in specific quantum gates or qubits through independent layer evaluation. Simulation results demonstrate that the proposed method improves circuit fidelity by an average of 6.8% and 4.1% compared to Layer Randomized Benchmarking and Interleaved Randomized Benchmarking methods in a thermal relaxation noise environment, and by 40% compared to Layer RB in a bit-flip noise environment. Moreover, the method detects preset faulty quantum gates in circuits generated by the Munich Quantum Toolkit Benchmark, verifying the model's validity and providing a new tool for faulty gate detection in quantum circuits.

Routing design is an important aspect in aiding the completion of the Quantum Processing Unit (QPU) layout design for large-scale superconducting quantum processors. One of the research focuses is how to generate reliable routing schemes within a short time. In this study, we propose a superconducting quantum processor auto-routing method for supporting scalable architecture, which is mainly implemented through the bidirectional A star algorithm, the backtracking algorithm, and the greedy strategy. By using this method, the number of crossovers and corners can be reduced while efficiently completing the processor routing. To verify the effectiveness of our method, we selected 5 types of qubit numbers for processor routing experiments. The experimental results show that compared to the improved A star algorithm of Qiskit Metal, our method reduces the average execution time by at least 43.61% and 41.68% in serial and parallel, respectively. Compared with four other routing algorithms, our method has a minimum average reduction of 10.63% and 1.21% in the number of crossovers and corners, respectively. In addition, our method supports the processor routing design of planar and flip-chip architectures, and can automatically process both airbridge and insulation types of crossovers. Therefore, our method can provide efficient and reliable automated routing design to assist the development of large-scale superconducting quantum processors.

The decoherence effect of the real quantum computer poses a significant challenge for designing quantum neural networks (QNN), which requires simultaneous consideration of model performances and parameterized quantum circuit (PQC) scales. In this paper, a method for the intelligent generation of lightweight QNN is proposed, which utilizes the parameters of quantum chips such as topology and relaxation time to assist the automatic design of QNNs. Combining the mixture expert mechanism with the Hyperband algorithm, a Mixture of Hyperband Experts for QNN is proposed to search for combinations of hyperparameters that meet multi-objective requirements from the lightweight QNN. To the best of the authors' knowledge, this is the first work that combines quantum chip capabilities to intelligently generate lightweight QNNs. Experiments are carried out on datasets in the fields of medicine and information security, and compared with classical machine learning algorithms and quantum machine learning algorithms (QSVM, QKNN, Intelligent Generation for QNN), the QNN automatically generated by this method has good performance and scalability, and the PQC has a smaller scale. The anti-coherence capability of the QNN intelligently generated by this method is verified using experiments on a real quantum computer.

The intrinsic parasitic longitudinal (ZZ) coupling between coupled qubits degrades the fidelity of quantum gate operations, becoming a major limiting factor for building large-scale, scalable superconducting quantum chips. Therefore, it is essential to develop a coupling scheme that can flexibly control the ZZ interaction. This work proposes a simple coupling architecture that enables high-fidelity quantum gate operations via tunable ZZ coupling. The scheme leverages a bus resonator with anharmonicity to effectively suppress the ZZ coupling between two frequency-tunable Xmon qubits. Moreover, theoretical demonstrations show that the ZZ interaction can be tuned via qubit frequency adjustment, thus enabling two-qubit controlled-Z (CZ) gates. Finally, the fidelity of gate operations is evaluated using cross-entropy benchmarking, realizing a CZ gate fidelity of (99.310.04)%. This work demonstrates flexible ZZ coupling control without increasing circuit complexity, offering a new paradigm for the development of large-scale superconducting quantum processors with simplified control wiring.

Continuous-variable source-independent quantum random number generator (CV-SI-QRNG) can produce random numbers with an untrusted source. However, the material properties of trusted measurement devices may lead to potential security risks, such as Lithium niobate (LiNbO 3 , LN) devices, which must be accurately characterized and considered in security analysis. The performances of LN devices are sensitive to photorefractive effect (PE) in LN, which has been shown to be exploited for malicious attacks on quantum key distribution. However, the research on the security problems associated with loopholes induced by PE has not been carried out in the practical security of CV-SI-QRNG. In this paper, we give a light-induced photorefraction attack against homodyne-based CV-SI-QRNG as well as the corresponding security analysis. Simulation results show that eavesdroppers can use very weak irradiation beam to change the splitting ratio of directional coupler and the phase shift of phase modulator, which leads to an overestimation on the number of extractable random bits. Our work reveals that PE-related security issues should be carefully considered in the LN-based QRNG.

Optimizing the architecture of superconducting quantum processors is crucial for improving the efficiency of executing quantum programs. Existing schemes either modify general-purpose architectures, which might lead to an increase in the probability of qubit frequency collisions, or customize special-purpose architectures based on the quantum programs to reduce the gate operations after qubit mapping, but the architectures lack support for the post-mapping gate operations’ optimization of multiple programs, which reduce their reusability. In this study, we propose a new processor architecture design method that reduces the average growth of the total post-mapping gate count on multiple quantum programs as well as to reduce the impact of processor architecture on frequency collisions, and thus improve the reusability of special-purpose processor. The main idea is to construct a new architecture by finding maximum common edge subgraph among multiple special-purpose processor architectures. To show the effectiveness of our method, we selected quantum programs with different functions covering 9 types of qubit numbers for comparison. Comprehensive simulation results show that the architecture schemes generated by using our method outperform two general-purpose architecture schemes based on the square lattice and the eff-5-freq’s special-purpose architecture schemes, respectively. Compared to the all 2-qubit bus and the eff-5-freq’s architecture schemes, after qubit mapping, the architecture schemes of our method have the smallest average growth of gate operations in multiple quantum programs (the largest average growth is 5.63