A compact tunable band-pass filter designed for EEG, ECG, and EMG signal processing is introduced, featuring low power consumption and employing class-AB amplifiers along with high-value programmable active pseudo-resistors. These components are biased using the quasi-floating-gate technique with capacitive gate-voltage averaging, thereby reducing distortion. The filter, implemented in a three-stage design using 0.5 μ m CMOS technology and simulated with HSPICE, covers a tunable frequency range from 0.5 Hz to 3 kHz, operates on a bias current of 25 nA, and achieves a total harmonic distortion (THD) of 0.56

This work introduces the first four-quadrant CMOS analog multiplier circuit built entirely from digital inverter standard cells, without requiring any analog transistor-sizing methodologies. The multiplication operation is performed using a quadratic cancellation scheme in conjunction with a modified high-speed Nauta transconductor, which serves as summing point circuit. Consequently, the proposed multiplier achieves bandwidths of 2.2 GHz with x1 inverter cells and 3.8 GHz with x12 inverter cells, respectively. Additionally, the output offset issue is addressed by the same summing-point circuit. The power and silicon area consumption of both multipliers are 0.423 mW/( 7.6 mu m x14.73 mu m) and 5.075 mW/( 17.8 mu m x14.73 mu m), respectively. Mathematical modeling and post-layout transistor-level simulations using a TSMC 65 nm CMOS process, with a BSIM4 level 54 model, successfully validate the proposed multiplier. Finally, because the multiplication architecture is entirely composed of CMOS inverters (NOT gates), this circuit can be implemented and scaled for any advanced technology node that includes a digital standard-cell library.

This paper presents a systematic gm/ID-based transistor-level design methodology for MOS M-2M ladder digital-to-analog converters (DACs) targeting low-power operation with predictable linearity. The proposed design methodology establishes an explicit relationship between inversion level, device geometry, mismatch-induced current errors, and static linearity while enforcing triode-region operation to ensure accurate binary current division. A two-dimensional (gm/ID, L) design-space exploration integrates mismatch constraints, operating-region limits, and current-density information extracted from technology lookup tables. The methodology is validated through 5-bit and 8-bit M-2M DAC implementations in 65-nm CMOS technology. The prototypes achieve power dissipation of 2.44 mu W and 11.8 mu W, respectively, while maintaining worst-case DNL/INL within +/- 1.12 LSB and dynamic performance up to 6.7 ENOB and 48.834 dBFS SFDR at 1 MS/s. The resulting designs achieve energy efficiencies as low as 0.081 pJ/step and compact estimated core areas down to 1.84 & times; 10-4 mm2. These results demonstrate that the proposed gm/ID-guided methodology provides insight into the design of MOS ladder DACs, enabling favorable trade-offs among energy efficiency, silicon area, and linearity in low-to moderate-resolution mixed-signal systems.

The Clapp oscillator consists of one voltage amplifier, one inductor, three capacitors, and three resistors. The proposed work analyses the Clapp oscillator when two resistors are replaced by a commercially available physical memristor, e.g. the Knowm memristor, and a third case when the polarity of the memristor is inverted. In this manner, three cases are analyzed and compared with the responses of the Clapp oscillator without a memristive element. The responses of the experiments show how the position and polarity of the Knowm memristor influence the steady-state behavior of the LC resonant oscillator. The results show that the three cases, using the Knowm memristor, produce measurable changes in frequency of oscillation, amplitude, and temporal symmetry of the output waveform, whereas reversing the memristor polarity, reverses both frequency and temporal asymmetry trends. As a conclusion, the observed behaviors indicate that the memristor acts as a dynamic and history-dependent element, i.e. it modifies the oscillation conditions of the Clapp oscillator beyond the effects of a static resistive component. These findings establish that the Clapp oscillator topology, is a suitable experimental platform for studying memristive effects in LC resonant systems. The results provide insights into the role of memristive devices position and polarity in shaping oscillatory dynamics.

This work introduces a tunable technique to push the low-frequency corner (fL) of capacitively coupled instrumentation amplifiers (CCIAs) to the sub-mHz range for emerging biosensing applications. The proposed approach combines Complementary Transimpedance Boosting (CTB) to limit the DC feedback current and segmented duty-cycled resistors (SDR) for tunable resistance. The CTB-SDR technique achieves a stable effective post-layout pseudo-resistance of 535.8 T Omega, equivalent to fL=660 mu Hz while occupying 0.062 mm2 in a 180 nm process. According to JESD91 standards, it shows a standard deviation of 0.19 mHz under post-layout Monte Carlo + process analysis, 1.1% spread under voltage variations (+/- 5.56% VDD) and 6.2% under temperature variations (-20 degrees C, 27 degrees C, and 60 degrees C). In addition, duty-cycling calibration can compensate for worst-case process corner variations and mismatch-induced feedback instability.

This work tests and confirms the capability of the Particle Swam Optimization (PSO) algorithm to find the equalization coefficients used in High-Speed Serial Interfaces (HSIO) to compensate the channel frequency dependent losses. To test the algorithm, a HSIO system with a Feed-Forward Equalizer (FFE), Continuous Time Linear Equalizer (CTLE) and Direct Feedback Equalizer (DFE) were modeled and tested for channels with different losses. Results indicate that the PSO algorithm successfully obtain the optimal equalization coefficients simultaneously.

This work shows the development of an electrocardiogram (ECG) data masking system based on double-scroll synchronized chaotic oscillators. The contribution is devoted to the introduction of a CMOS implementation of a double-scroll chaotic oscillator, which is designed by taking advantage of the intrinsic hyperbolic tangent-type characteristic of the operational transconductance amplifier (OTA). The chaotic behavior of the CMOS oscillator is guaranteed by plotting the bifurcation diagram and evaluating the Lyapunov exponents. In this manner, a masking system based on CMOS chaotic systems is designed to protect privacy while transmitting ECG signals effectively. Basically, the chaotic time series is processed to generate pseudorandom signals in a continuous-time domain. Mathematical modeling and simulation results under a UMC 180-nm CMOS fabrication process demonstrate that the proposed masking system is well suited to provide hardware-level security in the chaotic encryption of biomedical signals.

The proposed work introduces a low-power ring oscillator architecture that achieves enhanced tunability by incorporating quasi-floating gate transistors (QFGTs) into a modified Maneatis delay cell. The proposed CMOS design features a local feedback mechanism at the load node, which establishes a summing point at the complemented output through the QFGTs configuration. The capacitive divider ratio associated with the QFGT structure defines a programmable feedback factor (beta), allowing flexible control of the phase delay and consequently of the oscillation frequency. The proposed circuit is mathematically modeled and validated through simulations using a TSMC 180 nm CMOS process. Evaluations are performed through 500-run Monte Carlo simulations and analyses of process corner variations to assess robustness.

This work describes MexSIC, a data acquisition channel designed for Silicon Photomultipliers (SiPMs), composed of a mixed-mode application specific integrated circuit (ASIC) front-end, an FPGA-based processing stage, and a user interface. The ASIC provides a 1-bit sigma-delta modulated (ΣΔ – M ) digital equivalent of the input SiPM current, a flag indicating the start/end of the SiPM pulse, and a clock reference generated by an internal Phase Locked Loop (PLL). At the ASIC input stage, the SiPM current is converted to voltage by means of a 1.57 GHz bandwidth transimpedance amplifier (TIA), the gain of which can be switched between 21 dB and 48 dB, allowing for an input current range between 20 μ A and 20 mA. The generated voltage signal is then fed to a Triggering Unit (TU) implemented to discriminate between desired signals and the spurious ones, and in parallel, also to a second-order ΣΔ modulator providing 6.1 Equivalent Number Of Bits (ENOB). The TU circuit sends a start/end bit flag by comparing the SiPM voltage signal with an 8-bit programmable voltage reference. The ΣΔ was selected to have a single output line instead of using a data bus with many lines, which is important in applications where the number of SiPM channels being read out is very large. The 10 MHz bandwidth ΣΔ – M uses an Over Sampling Ratio (OSR) of 50, and a 1 GHz sampling clock that is generated by a PLL using an off-chip 100 MHz reference. The FPGA receives the ASIC ΣΔ modulated output signal and performs a decimation process by means of a Cascade Integrator Comb (CIC) filter to complete the data recovery. The recovered signal is visualized in a Matlab programmed Graphical User Interface (GUI). The MexSIC ASIC was designed in a 180 nm CMOS standard process using Cadence © software, and the processing stage was implemented in a Kintex-7 FPGA.

This paper presents two classic analog oscillators: a relaxation oscillator and a Wien bridge one, where a memristor replaces a resistor. The circuits are simulated in TopSPICE 7.12 using a memristor emulation circuit and commercially available components to evaluate the memristor’s impact. In the case of the relaxation oscillator, which includes the memristor, a notable increase in oscillation frequency was observed compared to the classical circuit, with a nearly 10-fold increase from 790 Hz to 7.78 kHz while maintaining a constant amplitude. This confirms the influence of the memristor’s dynamic resistance on the circuit time constant. On the other hand, the Wien-bridge oscillator exhibits variations in specific parameters, such as peak voltage, amplitude, and frequency. In this case, the oscillation frequency decreased from 405 Hz to 146 Hz with the addition of the memristor, a characteristic introduced by the proposed memristive element’s nonlinear interactions. Experimental results confirm the feasibility of incorporating memristors into classical oscillator circuits, enabling frequency changes while maintaining stable oscillations, allowing reconfigurable and adaptable analog designs that leverage the properties of memristive devices.

This work presents a ring oscillator design flow that calculates the transistor's dimensions and bias currents that meet the oscillation frequency and phase noise requirements using only pre-calculated tables and MATLAB scripts. The methodology combines look-up tables, the gm/ID methodology, and the square root of the delay K. Results indicate a significant correlation between calculation and simulations with a variation percentage of the frequency oscillation from 2.3% up to 29% for oscillators designed in a TSMC 180 nm CMOS technology.

This work presents a reconfigurable-band analog filter capable of performing the low-pass, high-pass, band-pass or all-pass functions. The proposed filter is a simple and compact cell composed of only two RC networks and one differential Operational Transconductance Amplifier (OTA). To select the desired filter type, two configurations must be done: 1) the two RC network shall be configured as low-pass/low-pass, high-pass/high-pass or low-pass/high-pass, 2) the input signals must be fed in differential or single mode. To validate theory and simulations, the proposed reconfigurable-band filter was designed, fabricated and measured to meet the biomedical band (0.1 Hz - 10 kHz) in a 0.5 μm CMOS standard fabrication process. To achieve the extremely low RC time constants imposed by the biomedical band, the R element was implemented using PMOS high-value programmable resistor. The prototype exhibits a silicon area of 470 μm x 250 μm and a power consumption of 96.32 μW using a ± 0.8 V symmetric power supply. Due to this circuit’s ability to perform four filter-functions, its operation band can be tuned over five decades, its power consumption is in the nano and micro-watt regime, and it is area compact, the proposed analog filter is a suitable candidate for being an analog standard-cell.

This manuscript shows the CMOS design of Lorenz systems using operational transconductance amplifiers (OTAs). Two Lorenz systems are then synchronized in a master–slave topology and used to implement a CMOS secure communication system. The contribution is devoted to the correct design of first- and second-order OTA-C filters, using 180 nm CMOS technology, to guarantee chaotic behavior. First, Simulink is used to simulate a secure communication system using two Lorenz systems connected in a master–slave topology, which is tested using sinusoidal signals that are masked by chaotic signals. Second, the Lorenz systems are scaled to have amplitudes of the state variables below 1 Volt, to allow for CMOS design using OTA-C filters. The transconductances of the OTAs are tuned to accomplish a Laplace transfer function. In this manner, this work highlights the design of a second-order CMOS OTA-C filter, whose damping factor is tuned to generate appropriate chaotic behavior. Finally, chaotic masking is performed by designing a whole CMOS secure communication system by using OTA-C based Lorenz systems, and its SPICE simulation results show its appropriateness for hardware security applications.

This work presents a ring oscillator design flow that calculates the transistor’s dimensions and bias currents that meet the oscillation frequency and phase noise requirements using only pre-calculated tables and MATLAB scripts. The methodology combines look-up tables, the g m / I D methodology, and the square root of the delay K. Results indicate a significant correlation between calculation and simulations with a variation percentage of the frequency oscillation from 2.3% up to 29% for oscillators designed in a TSMC 180 nm CMOS technology.

This study rigorously investigates the effectiveness of nonlinear filters in CMOS for 2-D signal processing to enhance image quality. We comprehensively compare traditional linear filters’ performance, which operate on the principle of linearity, with nonlinear filters, such as the median-median (Med-Med) approach, designed to handle nonlinear data. To ensure the validity of our findings, we use widely accepted metrics like normalized squared error (NSE), peak signal-to-noise ratio (PSNR), and structural similarity index (SSIM) to quantify the differences. Our simulations and experiments, conducted under controlled conditions, demonstrate that nonlinear filters in CMOS outperform linear filters in removing impulse noise and enhancing images. We also address the challenges of implementing these algorithms at the hardware level, focusing on power consumption and chip area optimization. Additionally, we propose a new architecture for the Med-Med filter and validate its functionality through experiments using a 9-pixel image sensor array. Our findings highlight the potential of nonlinear filters in CMOS for real-time image quality enhancement and their applicability in various real-world imaging applications. This research contributes to visual technology by combining theoretical insights with practical implementations, paving the way for more efficient and adaptable imaging systems.

Nowadays analog-to-digital converters (ADCs) are widely used and can be found in various applications that require the conversion of analog signals to the digital domain. Despite the abundance of literature on ADC design, there is little information regarding the accurate characterization of these devices, resulting in common errors when simulating and determining their key parameters, especially for the most important one, the effective number of bits (ENOB). This papers provides a comprehensive guide on the proper characterization of the ENOB in ADCs. Also, this work highlights the most common errors during the acquisition and processing of the output data coming from the ADC's simulation.

Abstract A three‐stage rail‐to‐rail bulk‐driven class AB OTA that operates with ±0.15 V supplies and a power dissipation of 90 nW is introduced. The first two stages use resistive local common mode feedback. The OTA uses simple phase lead compensation. It has a 36 MHz.pF/μW small signal figure of merit and a 55(V/μs) pF/μW large signal figure of merit.

This work presents a Time-to-Digital Converter implemented using two nested Johnson counters and suitable for time-lapse measurement applications. The proposed structure is composed of two 4-bit nested counters, two digital-logic control networks, two registers and a single decoder. Semi-dynamic logic was used for the decoder to reduce its power consumption. The system has a standard digital output and is powered by a 1.8 V supply with a total power consumption of 32.4 mW. A prototype was fabricated using a TSMC 180 nm CMOS technology. The proposed structure uses a 508 µm x 225 µm area. In addition, this TDC has a standard deviation of 0.78 LSB with a fixed input time interval operating at a frequency of 1 MHz. The proposed structure shows good performance results and repeatability for continuous conversion conditions, these results are attributed to the simplicity of the system and the use of counters with minimum gate delay as the main elements for the TDC.

A comparative study of one-stage-amp performance improvement based on simulations in 22 nm, 45 nm, 90 nm, and 180 nm in deep submicrometer CMOS technologies is discussed. Generic SPICE models were used to simulate the circuits. It is shown that in all cases a simple modification using resistive local common mode feedback increases open-loop gain and gain-bandwidth product, peak output currents, and slew rate by close to an order of magnitude. It is shown that this modification is especially appropriate for its utilization in current CMOS technologies since large factor improvements were not available in previous technologies. The OTAs with resistive local common mode feedback require simple phase lead compensation with a very small additional silicon area and keep supply requirements and static power dissipation unchanged.

This work presents an 8-bit Time-to-Digital Converter (TDC) suitable for time-lapse measurement applications. The proposed TDC is composed of two nested 4-bit counters, a digital-logic control network, a register, and a decoder. Verilog language was used to synthesize the TDC using the standard cells of the technology. The system has a standard digital output and it is powered by a 1.8 V supply with a total power consumption of 9.86 mW. The characterization was performed by means of post-layout simulations using a TSMC 180 nm CMOS technology. The proposed structure exhibits a 355.4 μm × 105.8 μm area. In addition, this TDC has a standard deviation of 0.66 LSB with a fixed input time interval with a user-select operation frequency from 1 MHz to 1 GHz.