With the rapid advancement in information technology, embedded systems have become integral to a wide range of critical applications. These systems often require continuous operation and cannot tolerate the downtime associated with traditional software updates, which typically necessitate a system reboot. To address this challenge, this paper proposes a novel hotpatching technique called Flexible Linked EXecution (FLEX) designed specifically for real-time embedded environments. FLEX enables seamless, dynamic firmware updates by redirecting all function calls and global variable accesses through a compile time generated Control Flow Table (CFT). In contrast to existing hotpatching approaches that depend on specialized hardware or impose strict limits on the number of patches and their size, FLEX is entirely hardware independent and supports scalable patching capacity bounded only by available flash memory and RAM. FLEX offers several unique features, including a relaxed consistency state synchronization mechanism to allow for gradual migration of program state, resolving all symbols at compile time into CFT indirections, applying updates via a double-buffered pointer swap to a new CFT, and a XIP compatible process that guarantees only a short, bounded pause time regardless of patch complexity. Experimental results show that FLEX maintains system stability and performance with an average execution overhead of about 11% and a predictable increase in flash memory usage of roughly 17%. These findings suggest that FLEX offers a robust and flexible solution for dynamically updating the software of embedded systems to ensure high availability and security without sacrificing performance.

Recently, Unmanned Aerial Vehicles (UAVs), which are embedded, real-time systems, are being used in various fields such as military, logistics, surveillance, and mapping. UAVs face security threats due to their diverse peripherals and attack vectors. Real-world incidents, such as GPS spoofing and control signal manipulation, highlight the need for improved security systems in UAVs to prevent potential human losses and material damage. While prior research has examined UAV security vulnerabilities, it has primarily focused on individual attack techniques rather than systematically analyzing the relationship between software and hardware security risks. As such, effectively addressing these security threats necessitates a comprehensive analysis of the software and hardware architecture of UAVs and a systematic investigation of existing attack cases. This paper systematically analyzes UAV attack cases and defines a generalized UAV architecture based on commercial and open-source UAV platforms. Furthermore, we evaluate the security vulnerabilities in widely used UAV software frameworks, including PX4 Autopilot and the MAVLink communication protocol. Based on our findings, we propose a Secure UAV architecture leveraging ARM Platform Security Architecture (PSA) to enhance resilience against cyber threats.

Embedded systems rely on real-time operating systems (RTOS) for safety-critical applications, but the absence of fine-grained memory protection poses serious security risks. Existing protection mechanisms either require specialized hardware or rely on static configurations that fail to adapt to dynamic task behavior. This article introduces runtime enforcement of memory access protection (REMAP), which is a novel framework that combines LLVM-based static analysis with runtime memory protection unit (MPU) reconfiguration to achieve fine-grained, dynamic compartmentalization for RTOS environments. REMAP constructs task-specific access control table (ACT) at compile time and enforces them at runtime through on-demand MPU updates triggered by memory access violations. This lazy mapping strategy allows REMAP to support hundreds of compartments per task despite the limitation on the number of hardware MPU slots. Our prototype on ARMv8-M (Cortex-M33) demonstrates that REMAP enforces memory access control down to the function and variable level, protects shared buffers for secure inter process communication (IPC), and prevents error propagation across tasks. Evaluation using the BEEBS benchmark suite shows that compartment merging significantly reduces fault frequency, yielding overheads under 5% across all benchmarks. Therefore, REMAP achieves precise, adaptive memory protection suitable for commercial RTOS deployments without compromising real-time performance.

This paper proposes Filetype and Application aware Write-buffer management (FAW), the first technique to reduce the Write Amplification Factor (WAF) solely through the SSD's internal write buffer. Using lightweight host hints on filetype and application, FAW clusters pages that tend to be invalidated together within the same erase block and applies a Greedy-LR U policy across Hot and Cold segments to minimize garbage-collection-induced rewrites. In simulation, FAW reduces WAF by 86.61 % on synthetic mixed workloads and by 79.02% on real workloads (from 4.83 to 1.01) without significant latency penalties, corresponding to an estimated 4.8 x increase in SSD lifetime under real-world conditions. Measurements on production data-center SSDs confirm that WAF closely tracks throughput under sequential vs. random writes, demonstrating that controller-level placement guided by compact host hints can substantially improve both endurance and sustained performance without host-side redesign.

Bare-metal IoT devices, lacking memory management features such as virtual memory and Memory Management Units (MMUs), are increasingly vulnerable to memory corruption attacks like buffer overflow and Return-Oriented Programming (ROP). To address these challenges, this paper proposes the Segmented Stack Randomization (SSR) scheme, a novel approach that enhances security by randomly allocating stack space across multiple segments during function calls. Designed to operate without additional hardware, the proposed SSR is highly suitable for resource-constrained IoT environments, particularly those requiring predictable execution times for real-time applications. The proposed SSR involves Low Level Virtual Machine (LLVM)-based code instrumentation, enabling seamless integration into finalized firmware without introducing debugging complexities. A proof-of-concept implementation on an ARM Cortex-M4 platform demonstrated that SSR provides robust protection against stack-based attacks with minimal performance overhead, averaging 1.591 mu sec per function call. Additionally, the proposed SSR offers tunable trade-offs between memory usage and randomization entropy, ensuring adaptability to various application requirements. These results highlight the proposed SSR as a practical and efficient security solution for safeguarding bare-metal IoT devices against evolving threats.

Caches (and cache hierarchies) are an important aspect in modern hardware design. Caches also have a strong influence in the security of a modern platform, and in recent years there was a wave of new speculative side-channels discovered since the class was unveiled [1].This paper discusses reverse engineering techniques used by the authors to identify relevant cache characteristics that are necessary to mount some of the recently disclosed speculative side-channel attacks. The techniques are then applied on the latest interaction of Intel’s Hardware mitigation eIBRS (the "enhanced" IBRS), uncovering how it really works and how it differs, even if subtly, from the mitigations it is said to replace - retpoline (having weaknesses never discussed before). The findings open a new area for research in the speculative side-channels and how they are mitigated.

The rapid expansion of the Internet of Things (IoT) has led to increased concerns regarding the security of IoT systems. Attacks targeting IoT devices, such as code injection and code reuse, have become more sophisticated, compromising device control and functionality. Existing security schemes, designed primarily for the ×86 architecture, are not well-suited for resource-constrained IoT devices. While numerous studies aim to strengthen IoT device security, practical implementation faces challenges due to time-to-market requirements and manufacturing costs. To address these issues, this paper proposes an Augmented Security Module (ASM) that provides essential security services for IoT devices within the same network, requiring minimal device modifications. The ASM includes Hardware Security Modules (HSMs) like Trusted Platform Module (TPM) and Secure Element (SE) to ensure data integrity and execute requested security services. By adding ASM Agents, which perform minimal operations to request security services, IoT devices can easily access the provided security services. The proposed ASM enables flexible adaptation to evolving security requirements at a low cost, meeting practical manufacturing and time-to-market demands. To validate the effectiveness of the proposed ASM, four representative scenarios are presented and analyzed, demonstrating its ability to enhance IoT device security and prevent attacks. The proposed ASM contributes to the widespread adoption of secure IoT systems by ensuring the security of IoT devices within the network.

CFDP and PFCD page allocation schemes are commonly adopted for datacenter SSDs. However, they have limitations on improving read performance as their fixed allocation unit of a single page causes the layout of related data to be dispersed. This paper proposes the Dynamic Clustering Page Allocation scheme, which dynamically adjusts the allocation unit by considering the characteristics of application-level I/Os to find an optimal trade-off between the utilization of channel-level parallelism and internal flash-chip features. Our simulation study shows that the DCPA scheme improves throughput for read-intensive applications compared to CFDP/PFCD by a factor of 1.59 - 3.15.

The proliferation of IoT comes with many challenges, among which security is one of the most serious issues. Since most IoT devices are designed based on bare-metal devices with low performance, low power, and small form factor, an attacker can easily perform firmware extraction and analysis. In addition, code reuse attacks, such as Return Oriented Programming (ROP) attacks, are possible based on the analyzed firmware information. Since most code reuse attacks are performed through a combination of gadgets that include return instructions, preventing an attacker from analyzing return instructions can be a fundamental solution for these attacks. To prevent code reuse attacks on bare-metal based IoT devices, this paper proposes Return Instruction Obfuscation (RIO). The proposed scheme encrypts all return instructions in the firmware and instruments the modules necessary to decrypt and execute the encrypted return instructions using a Low Level Virtual Machine (LLVM). Since all return instructions in the firmware are encrypted, the proposed scheme can prevent attackers from performing firmware analysis and gadget collection. The proposed scheme was implemented and evaluated on Nuvoton’s NuMaker-PFM-M2351 development board with an ARM Cortex-M23 based SoC.

Caching is an important technique to speed-up execution, and its implementation and use cases vary. When applied specifically to the memory hierarchy, caching is used to speed up memory accesses and memory translations. Different cache implementations are considered microarchitectural secrets and oftentimes change between generations. The integration of caches in hardware greatly influences security policy enforcement in the platform since caches maintain copies of code and data and their security properties. Examples of attacks due to the existence of caches are side-channels against cryptographic software, recent speculative execution abuses to leak secret data, and usages of cache-based manipulations (e.g., forcing cache splits/incoherence) to hide from security software detection. This survey examines the security issues due to different cache usages in a microarchitecture. The survey also explains the most complicated caching features and their impact on the security of the platform in different scenarios.

This paper proposes the Cost-Age-Time Data Organized Garbage Collection (CATDOG) scheme, which clusters data based on their update frequencies to reduce the overhead of data migration. It also trades off between endurance and throughput, and efficiently erases multiple blocks to reduce garbage collection latency. To the best of our knowledge, this is the first paper to provide a holistic discussion on the effects of combining all three factors. Our simulation study shows that CATDOG achieves a maximum of 3.54 times higher throughput performance and 1.18 times greater endurance than a selected baseline for a heavy write workload.

This paper proposes a new Flash Translation Layer (FTL) scheme that improves the performance of SSDs by minimizing resource contention. This is achieved by holistically managing all the FTL issues such as page allocation, garbage collection, wear leveling, and scheduling to maintain load balancing. The proposed ReCA-FTL consists of Resource Balancing Allocation, Erasure Counts Balancing Garbage Collection, Hot/Cold-Pool Balancing Wear Leveling, and Resource Contention Cost based Scheduling. The RBA, ECB GC, and H/C-PB WL schemes are designed to balance the number of free pages, erasure counts, recent erasure counts, and the hot/cold pool membership. The RCCS scheme reschedules jumbled incoming requests to utilize advanced flash-chip commands. This alleviates resource contention allowing SSDs to utilize all the resources more effectively. Our detailed simulation study shows that the proposed FTL scheme provides on average of 1.75 and maximum of 2.04 times higher throughput than a selected baseline for a variety of workloads.

A cognitive radio (CR) is a promising technology to solve the emerging spectrum crisis, especially for applications where thousands of wireless sensor nodes are deployed. Since continuous spectrum sensing will greatly reduce the lifetime of a network composed of energy-restricted CR nodes, an accurate method for predicting spectrum occupancy is necessary to improve energy efficiency. This paper proposes a hidden Markov model (HMM)-based cooperative spectrum sensing (CSS) that predicts the status of a network environment. The traditional prediction algorithms for cooperative spectrum sensing assume that all CR nodes have the same network environment. However, the channel availability of various CR nodes can be quite different, and thus the traditional algorithms will lead to low prediction accuracy in a complex radio environment. The proposed methods learn the historical spectrum sensing results and help the network to make an energy-efficient spectrum sensing decision. More specifically, the hidden state of HMM is set to different areas, where primary users (PUs) perform different activities. A Baum-Welch (BW) algorithm is employed to estimate the parameters of the HMM based on the past spectrum sensing results, and then the parameters are fed to a forward algorithm for the predicting of PUs’ activity. Based on the prediction, secondary users (SUs) are classified into either "interfered by PU" or "not interfered by PU." The nodes selected as "interfered by PU" will not perform spectrum sensing to reduce unnecessary energy consumption. The performance of the proposed method is evaluated using the simulations under different traffic conditions. The simulation results show that, compared with the conventional HMM-based methods, the effectiveness of the proposed algorithm in energy efficiency and spectrum utilization improved by about 13% and 15%, respectively. INDEX TERMS Cognitive radio, hidden Markov model, spectrum sensing, energy efficiency.

Recent IoT services are being used in various fields such as smart homes, smart factories, smart cars and industrial systems. These various IoT services are implemented through hyper-connected IoT devices, and accordingly, security requirements of these devices are being highlighted. In order to satisfy the security requirements of IoT devices, various studies have been conducted such as HSM, Security SoC, and TrustZone. In particular, ARM proposed Platform Security Architecture (PSA), which is a security architecture that provide execution isolation to safely manage and protect the computing resources of low-end IoT devices. PSA can ensure confidentiality and integrity of IoT devices based on its structural features, but conversely, it has the problem of increasing development difficulty in using the security functions of PSA. To solve this problem, this paper analyzes the security requirements of an IoT platform and proposes secure platform based on PSA. To evaluate the proposed secure platform, a PoC implementation is provided based on hardware prototype consisting of FPGA. Our experiments with the PoC implementation verify that the proposed secure platform offers not only high security but also convenience of application development for IoT devices.

Adaptive bitrate (ABR) streaming algorithms play an important role in ensuring a high Quality of Experience (QoE) for the consumer. However, a lot of ABR algorithms tend to be too ad hoc. In response, methods based on a Markov Decision Process (MDP) offer more intelligent models. In particular, Reinforcement Learning (RL) methods typically do so via QoE metrics. However, RL methods are plagued by high complexity and long convergence times due to their model-free nature. This paper proposes qMDP, which is an RL method with an MDP partially modeled by an M/D/1/K queue. Our study shows that qMDP results in higher QoE and faster convergence compared to a QoE-only model-free version.

Virtualization-based technologies have become ubiquitous in computing. While they provide an easy-to-implement platform for scalable, high-availability services, they also introduce new security issues. Traditionally, discussions on security vulnerabilities in server platforms have been focused on stand-alone (i.e., non-virtualized) environments. For cloud and virtualized platforms, the discussion focuses on the shared usage of resources and the lack of control over the infrastructure. However, the impact virtualization technologies can have on exploit mitigation mechanisms of host machines is often neglected. Therefore, this survey discusses the following issues: first, the security issues and challenges that are introduced by the migration from stand-alone solutions to virtualized environments—special attention is given to the Virtual Machine Monitor, since it is a core component in a virtualized solution; second, the impact (sometimes negative) that these new technologies have on existing security strategies for hosts; third, how virtualization technologies can be leveraged to provide new security mechanisms not previously available.; and, finally, how virtualization technologies can be used for malicious purposes.

Video-streaming applications are very popular these days. Existing studies of video streaming have attempted to identify video titles of users using machine learning techniques to identify specific patterns of video packets transmitted over the network. However, these studies have limitations when applied to actual environments where the network is congested or there are multiple users in the same network. This paper proposes Video Title Identification using open Metadata(VTIM), which identifies video titles by analyzing storyboards and Media Presentation Description (MPD) of MPEG-DASH in connection with video packets transmitted over the network. Attack was carried out using VTIM on 13,291 videos selected from actual video-streaming environment of YouTube. Our experiments show that VTIM is able to identify video titles with 100% accuracy at nearly thirty times faster than existing methods based on machine learning techniques. The paper also proposes and evaluates a countermeasure against VTIM.

The Flexible Dual TCP-UDP Streaming Protocol (FDSP) combines the reliability of TCP with the low latency of UDP, thus providing transport layer improvements towards maintaining high QoE of multi-bitrate videos in adaptive streaming. FDSP delivers the more critical parts of the video data via TCP and the rest via UDP. FDSP also uses Bitstream Prioritization (BP), a sliding scale that determines the proportion of video data that is sent using TCP. BP can be adjusted according to the level of network congestion. FDSP-based streaming reduces total rebuffering time by over 90%, and rebuffering instances by 50% in many cases compared to TCP-based streaming. At the same time, packet loss reduces by over 75% for most BP levels compared to UDP-based streaming. In addition, FDSP-based streaming is potentially more suitable for adaptive streaming compared to the state-of-the-art TCP-based HTTP Adaptive Streaming (HAS), which is often plagued by high latency and high bandwidth requirements. In contrast, FDSP requires significantly less bandwidth than TCP in congested networks while exhibiting more stable client buffers.