Optimizer selection in deep neural networks fundamentally impacts not only training dynamics but also deployment-phase inference efficiency and energy consumption—critical considerations for autonomous maritime systems operating under stringent resource constraints. This study presents a comprehensive mathematical framework for evaluating five optimization algorithms (SGD, Adam, NAdam, RAdam, and Adadelta) across the complete deep learning lifecycle, from training convergence to edge deployment, applied to YOLO-based object detection for Unmanned Surface Vehicles (USVs). Through systematic experimentation on YOLOv8n and YOLO12n architectures across heterogeneous computing platforms (NVIDIA Tesla V100, A30, RTX 3090, and Jetson AGX Orin), we establish quantitative relationships between optimizer characteristics and multi-objective performance metrics encompassing detection accuracy (mAP$_{50}$, precision, recall), computational efficiency (training time, convergence stability), and deployment viability (inference latency, energy consumption, throughput). Statistical analysis of 120 independent training instances with early stopping mechanisms reveals that Adadelta and SGD achieve superior detection accuracy (0.89< P < 0.92) with exceptional stability (standard deviations $\sigma < 0.0074$) compared to adaptive learning rate methods. Critically, we demonstrate that optimizer choice affects inference characteristics: Adadelta-8n achieves optimal energy efficiency (19.84 FPS/W) on edge platforms while maintaining highest accuracy, whereas Adam-8n maximizes throughput (179.47 FPS) at 6.5\% accuracy cost. The A30 GPU demonstrates 24\% higher computational productivity (0.475 vs 0.383 mAP$_{50}$/hour) than the V100, though statistical analysis reveals no significant GPU $\times$ Optimizer interaction ($p > 0.05$), confirming hardware-invariant optimizer performance rankings. We introduce a composite operational efficiency score integrating accuracy and energy consumption, consistently identifying Adadelta-8n as optimal across the computing continuum (scores: 96.16--96.28). For extended missions, seemingly modest per-frame energy differences ($\approx$ 3\%) accumulate substantially: over 8-hour operations, optimizer selection impacts battery consumption by 10--15\%, establishing it as an architectural decision affecting mission feasibility. These findings demonstrate that optimizer selection constitutes a critical design parameter influencing the entire deployment lifecycle, with Adadelta emerging as the recommended choice for maritime applications prioritizing accuracy, stability, and energy efficiency in resource-constrained autonomous systems.

Julia is a high-level language that supports the execution of parallel code through various packages. CUDA.jl is widely used for developing GPU-accelerated code in Julia and is integrated into many libraries and programs. In this paper, we present Juliana, a novel tool that automatically translates Julia code utilizing the CUDA.jl package into an abstract, multi-backend representation powered by the KernelAbstractions.jl package. To evaluate the tool's viability and performance, we analyzed four Julia projects: Rodinia, miniBUDE, BabelStream, and Oceananigans.jl. The performance overhead of this approach was found to be relatively low (under 7% for the Rodinia suite), with performance portability metrics showing results nearly identical to the native implementations. By running the same code across multiple KernelAbstractions' backends, we successfully executed these translated projects on GPUs from vendors such as NVIDIA, Intel, AMD, and Apple. This ensured compatibility across these platforms and enabled first-time execution on some devices.

The high-performance computing (HPC) landscape is undergoing rapid transformation, with an increasing emphasis on energy-efficient and heterogeneous computing environments. This comprehensive study extends our previous research on SYCL's performance portability by evaluating its effectiveness across a broader spectrum of computing architectures, including CPUs, GPUs, and hybrid CPU-GPU configurations from NVIDIA, Intel, and AMD. Our analysis covers single-GPU, multi-GPU, single-CPU, and CPU-GPU hybrid setups, using two common, bioinformatic applications as a case study. The results demonstrate SYCL's versatility across different architectures, maintaining comparable performance to CUDA on NVIDIA GPUs while achieving similar architectural efficiency rates on AMD and Intel GPUs in the majority of cases tested. SYCL also demonstrated remarkable versatility and effectiveness across CPUs from various manufacturers, including the latest hybrid architectures from Intel. Although SYCL showed excellent functional portability in hybrid CPU-GPU configurations, performance varied significantly based on specific hardware combinations. Some performance limitations were identified in multi-GPU and CPU-GPU configurations, primarily attributed to workload distribution strategies rather than SYCL-specific constraints. These findings position SYCL as a promising unified programming model for heterogeneous computing environments, particularly for bioinformatic applications.

Julia is a high-level language that supports executing parallel code through various packages. CUDA.jl is prominently used for developing GPU Julia code across a significant number of libraries and programs. In this paper, Juliana, a new tool that translates Julia code utilizing the CUDA.jl package to an abstract multi-backend representation powered by the KernelAbstractions package, is presented. The performance impact of this translation is evaluated using a custom adaptation of the well-established Rodinia benchmark suite to Julia CUDA.jl. To ensure the viability of the tool from a performance perspective, an accurate statistical analysis of the overhead using the BenchmarkTools Julia package is performed, comparing the same benchmark code on the same CUDA device before and after the translation. Additionally, the portability of this approach is demonstrated by running the translated code across multiple backends of KernelAbstractions, allowing the execution of the Rodinia benchmark suite on different GPU vendors such as NVIDIA, Intel, AMD, or Apple.

Following the recent advances in open hardware generally, and RISC-V architectures particularly, we analyse the performance of transformer encoder inference on three low-power platforms with this type of architecture. For this purpose, we conduct a detailed profile of the inference process for two representative members of the BERT family, identifying the main bottlenecks and opportunities for optimisation on three RISC-V processors equipped with floating-point SIMD (single instruction, multiple data) units: XuanTie C906, C908, and C910.

Bioinformatics and Computational Biology are disciplines that have used GPUs for over two decades to accelerate data processing in computational applications, where CUDA has been the most utilized programming language. However, the exclusive use of CUDA presents a portability issue, as it is only compatible with NVIDIA GPUs and not with other heterogeneous architectures, such as AMD or Intel GPUs, or any other type of accelerator. To address this portability challenge, the Khronos Group recently introduced the SYCL standard, a multi-platform programming model that offers a high-level programming interface. This standard facilitates the development of portable applications that can efficiently leverage the capabilities of different hardware devices, such as NVIDIA, Intel, and AMD GPUs, without needing significant modifications to the source code. Therefore, this thesis set out as its general objective to evaluate the feasibility of SYCL as a unified, portable, and efficient heterogeneous programming model for the design and development of computationally demanding applications on heterogeneous GPU-based systems, specifically in the field of bioinformatics. Initially, a detailed investigation was conducted about heterogeneous programming models, performance metrics, and bioinformatics concepts, in order to establish the theoretical foundations of this thesis. Then, the SW# suite was chosen as the case study, as it represents a clear example of a CUDA-based bioinformatics application for biological sequence alignment. Using the SYCLomatic tool, a complete migration of the CUDA code to SYCL was carried out, which involved modifying the generated code and solving runtime errors. Additionally, the functionality was verified, optimizations were applied, and the resulting SYCL code was standardized to be compatible with other SYCL implementations. Subsequently, multiple experiments were conducted to evaluate the functionality and performance portability of the software migrated to SYCL. These experiments involved running the application on a wide variety of HPC platforms, including different CPUs and GPUs from various manufacturers. The results obtained demonstrated performance comparable to CUDA in most configurations, confirming the effectiveness of SYCL. Moreover, good performance portability across platforms was observed due to SYCL's ability to run on various hardware combinations. Furthermore, performance remained consistent when switching SYCL implementations. In conclusion, this study demonstrates that SYCL is a viable alternative as a unified, portable, and efficient programming model in the context of heterogeneous computing with GPUs for bioinformatics applications. The findings of this study lay the groundwork for the transition of legacy applications and the development of new solutions leveraging the capabilities of SYCL.

Edge computing stands as a crucial component of the IoT revolution. IoT benefits significantly from reduced latency, enhancing real-time applications, and time-sensitive processes. However, since edge platforms must be energy-efficient while maintaining high performance in real-time environments, exploiting accelerators becomes pivotal to reduce energy consumption while increasing performance. CUDA or HIP languages are widely used to program GPUs; however, they are limited to specific vendor platforms. In contrast, solutions such as SYCL or Kokkos could benefit from their ability to run across parallel multi-architecture.This paper explores the trade-offs of CUDA, SYCL, and Kokkos in three Edge platforms: Jetson AGX Orin, Jetson Orin Nano, and UP Squared Pro 7000 (Intel). The work conducts an analysis of the power modes of each platform and compares CUDA, SYCL, and Kokkos on those platforms.The experimental results revealed that, on average, there is an increased level of energy consumption compared to native solutions. Specifically, Kokkos demonstrated a 25% higher demand, whereas SYCL exhibited an average increase of 11%. These figures underscore the trade-off that programmers face in pursuit of achieving code portability when most performant solutions are non-crucial.

Bioinformatics and computational biology are two fields that have been exploiting GPUs for more than two decades, with being CUDA the most used programming language for them. However, as CUDA is an NVIDIA proprietary language, it implies a strong portability restriction to a wide range of heterogeneous architectures, like AMD or Intel GPUs. To face this issue, the Khronos group has recently proposed the SYCL standard, which is an open, royalty-free, cross-platform abstraction layer that enables the programming of a heterogeneous system to be written using standard, single-source C++ code. Over the past few years, several implementations of this SYCL standard have emerged, being oneAPI the one from Intel. This paper presents the migration process of the SW # suite, a biological sequence alignment tool developed in CUDA, to SYCL using Intel’s oneAPI ecosystem. The experimental results show that SW # was completely migrated with a small programmer intervention in terms of hand-coding. In addition, it was possible to port the migrated code between different architectures (considering multiple vendor GPUs and also CPUs), with no noticeable performance degradation on five different NVIDIA GPUs. Moreover, performance remained stable when switching to another SYCL implementation. As a consequence, SYCL and its implementations can offer attractive opportunities for the bioinformatics community, especially considering the vast existence of CUDA-based legacy codes.

Edge computing is essential to handle increasing data volumes and processing capacities. It provides real-time and secure data processing near data sources, like smart devices, alleviating cloud computing energy use, and saving network bandwidth. Specialized accelerators, like GPUs and FPGAs, are vital for low-latency edge computing but the requirements to customized code for different hardware and vendors suppose important compatibility issues. This paper evaluates the potential of SYCL in addressing code portability issues encountered in edge computing. We employed the Polybench suite to compare various SYCL implementations, specifically DPC++ and AdaptiveCpp, with the native solution, CUDA. The disparity between SYCL implementations was negligible, at just 5 ± 10% , depending on the application utilized. These gaps are the price one may need to pay when achieving the ability to successfully run the same code on two distinct edge boards. These findings underscore SYCL’s capacity to increase productivity in terms of development costs and facilitate IoT deployment without being locked into a particular platform or manufacturer.

The heterogeneous computing paradigm has led to the need for portable and efficient programming solutions that can leverage the capabilities of various hardware devices, such as NVIDIA, Intel, and AMD GPUs. This study evaluates the portability and performance of the SYCL and CUDA languages for one fundamental bioinformatics application (Smith-Waterman protein database search) across different GPU architectures, considering single and multi-GPU configurations from different vendors. The experimental work showed that, while both CUDA and SYCL versions achieve similar performance on NVIDIA devices, the latter demonstrated remarkable code portability to other GPU architectures, such as AMD and Intel. Furthermore, the architectural efficiency rates achieved on these devices were superior in 3 of the 4 cases tested. This brief study highlights the potential of SYCL as a viable solution for achieving both performance and portability in the heterogeneous computing ecosystem.

The aim of SYCL is to reduce the gap between the performance and code portability of the main accelerators used in HPC, such as multi-vendor CPUs, GPUs, and FPGAs. To evaluate SYCL’s performance portability, this paper uses the k -means algorithm as a case study. The k -means algorithm is simple to code but can be complex to optimize. In this research, we compare our developed SYCL version with the most efficient implementations of CUDA and OpenMP. Our resulting SYCL code can potentially run on multi-vendor CPUs and GPUs. Additionally, we have created a hand-tuned SYCL variation that is optimized for specific device architectures (CPU, NVIDIA GPU, and Intel GPU) to evaluate the performance difference between a standard version and an optimized one. The results show that SYCL outperforms Intel GPUs and CPUs compared to the state-of-the-art He-Vialle version, while on NVIDIA GPUs SYCL offers equivalent performance compared to its native CUDA implementation.

The aim of SYCL is to reduce the gap between the performance and code portability of the main accelerators used in HPC, such as multi-vendor CPUs, GPUs, and FPGAs. To evaluate SYCL’s performance portability, this paper uses the k -means algorithm as a case study. The k -means algorithm is simple to code but can be complex to optimize. In this research, we compare our developed SYCL version with the most efficient implementations of CUDA and OpenMP. Our resulting SYCL code can potentially run on multi-vendor CPUs and GPUs. Additionally, we have created a hand-tuned SYCL variation that is optimized for specific device architectures (CPU, NVIDIA GPU, and Intel GPU) to evaluate the performance difference between a standard version and an optimized one. The results show that SYCL outperforms Intel GPUs and CPUs compared to the state-of-the-art He-Vialle version, while on NVIDIA GPUs SYCL offers equivalent performance compared to its native CUDA implementation.

Python’s popularity has grown rapidly over the past decade due to its high productivity factor. While Python is popular in scientific computing, its interpreted nature and limitations on parallelization result in slower performance compared to compiled languages. Despite this, Python is still a valuable tool for high-performance computing (HPC) due to its ease of programming and optimization capabilities. This paper discusses the performance gap between Python and compiled languages like SYCL when working with heterogeneous computing environments and the challenges in developing portable and high-performance native extensions. It highlights the development of the dpctl Python library, which provides a portable and architecture-agnostic API for writing extensions and supports asynchronous SYCL kernel execution. We developed four benchmarks across CPU, integrated GPU, and discrete Intel Arc GPU, finding that SYCL outperformed Python in all cases, but optimizations could be made to improve Python performance. This research also highlights issues encountered when porting Python code, limitations in using Numpy, and current Intel Arc performance issues.

SYCL standard has been released with the conviction to increase code portability in heterogeneous environments. On its side, Intel has launched the oneAPI toolkit, which includes the Data Parallel C++ language, the Intel implementation of SYCL. SYCL is designed to use a single source code to target multiple accelerators, such as multi-core CPUs, GPUs, or even FPGAs. Additionally, the C/C++ oneAPI compiler also supports OpenMP which also allows targeting CPU and GPU devices. In this paper, a performance evaluation of SYCL and OpenMP is carried out using the well-known, Non-negative Matrix Factorization (NMF) algorithm. Three different NMF implementations (baseline, SYCL and OpenMP) are developed to analyze the speedups on both CPU and GPU devices. Experimental results show that while on CPUs both programming models report almost the same performance, on GPUs, SYCL slightly outperforms OpenMP counterpart.

Background and objectives: The computational biology area is growing up over the years. The interest in researching and developing computational tools for the acquisition, storage, organization, analysis, and visualization of biological data generates the need to create new hardware architectures and new software tools that allow processing big data in acceptable times. In this sense, heterogeneous computing takes an important role in providing solutions but at the same time generates new challenges for developers in relation to the impossibility of porting source code between different architectures.Methods: Intel has recently introduced oneAPI, a new unified programming environment that allows code developed in the SYCL-based Data Parallel C++ (DPC++) language to be run on different devices such as CPUs, GPUs, and FPGAs, among others. Due to the large amount of CUDA software in the field of bioinformatics, this paper presents the migration process of the SW# suite, a biological sequence alignment tool developed in CUDA, to DPC++ through the oneAPI compatibility tool dpct (recently renowned as SYCLomatic).Results: SW# has been completely migrated with a small programmer intervention in terms of hand-coding. Moreover, it has been possible to port the migrated code between different architectures (considering different target platforms and vendors), with no noticeable performance degradation.Conclusion: The SYCLomatic tool presented a great performance-portability rate. SYCL and Intel oneAPI can offer attractive opportunities for the Bioinformatics community, especially considering the vast existence of CUDA-based legacy codes.

In order to tackle the programming challenges related to heterogeneous computing, Intel recently introduced oneAPI, which is a new programming environment that allows code developed in the Data Parallel C++ (DPC++) language to be run on different devices such as CPUs, GPUs, and FPGAs, among others. To handle CUDA-based legacy codes, oneAPI provides a compatibility tool (dpct) that facilitates the migration to DPC++. In view of the large amount of existing CUDA-based software in the bioinformatics context, this paper presents our experiences porting SW#db, a well-known sequence alignment tool, to DPC++ using dpct. From the experimental work, it was possible to prove the usefulness of dpct for SW#db code migration and the cross-vendor GPU, cross-architecture portability of the migrated DPC++ code. In addition, the performance results showed that the migrated DPC++ code reports similar efficiency rates to its CUDA-native counterpart, or even better in some tests (by approximately 5%).

The Intel DPC++ Compatibility Tool is a component of the Intel oneAPI Base Toolkit. This tool automatically transforms CUDA code into Data Parallel C++ (DPC++), thus assisting in the migration process. DPC++ is an implementation of the programming standard for heterogeneous computing known as SYCL, which unifies the development of parallel applications on CPUs, GPUs or even FPGAs. This paper analyzes the DPC++ Compatibility Tool by considering the manual intervention required and the problems encountered while migrating the Rodinia benchmarks. For this suite, this tool achieves an impressive rate of almost 87% for code successfully migrated. Moreover, a comparative study of the performance obtained by the migrated code was carried out, showing a moderate overhead in most of the migrated examples. Finally, a performance comparison on different devices was also performed. (c) 2022 The Author(s). Published by Elsevier Inc.This is an open access article under the CC BY license (http://creativecommons.org/licenses/by/4.0/).

The SYCL standard was released to improve code portability across heterogeneous environments. Intel released the oneAPI toolkit, which includes the Data-Parallel C++ (DPC++) compiler which is the Intel’s SYCL implementation. SYCL is designed to use a single source code to target multiple accelerators such as: multi-core CPUs, GPUs and even FPGAs. Additionally, the C/C++ compiler provided in the oneAPI toolkit supports OpenMP which also allows targeting codes on both CPU and GPU devices. In this paper, the performance of SYCL and OpenMP is evaluated using the well-known non-negative matrix factorization (NMF) algorithm. Three different NMF implementations are developed: baseline, SYCL and OpenMP versions to analyze the acceleration on CPU and GPU. Experimental results show that while the two programming models perform almost identically on CPU, on GPU, SYCL outperforms its OpenMP counterpart slightly.

The heterogeneous computing paradigm represents a real programming challenge due to the proliferation of devices with different hardware characteristics. Recently Intel introduced oneAPI, a new programming environment that allows code developed in DPC++ to be run on different devices such as CPUs, GPUs, FPGAs, among others. This paper presents our first experiences in porting two CUDA applications to DPC++ using the oneAPI dpct tool. From the experimental work, it was possible to verify that dpct does not achieve 100% of the migration task; however, it performs most of the work, reporting the programmer of possible pending adaptations. Additionally, it was possible to verify the functional portability of the DPC++ code obtained, having successfully executed it on different CPU and GPU architectures.

High-Efficiency Video Coding (HEVC) is the new emerging video coding standard of the ITU-T Video Coding Experts Group (VCEG) and the ISO/IEC Moving Picture Experts Group (MPEG). The HEVC standard provides a significant improvement in compression efficiency in comparison with existing standards such as H264/AVC by means of greater complexity. In this paper we will examine several HEVC optimizations based on image analysis to reduce its huge CPU, resource and memory expensive encoding process. The proposed algorithms optimize the HEVC quad-tree partitioning procedure, intra/inter prediction and mode decision by means of H264-based methods and spatial and temporal homogeneity analysis which is directly applied to the original video. The validation process of these approaches was conducted by taking into account the human visual system (HVS). The adopted solution makes it possible to perform HEVC real time encoding for HD sequences on a low cost processor with negligible quality loss. Moreover, the frames pre-processing leverages the logic units and embedded hardware available on an Intel GPU, so the execution time of these stages are negligible for the encoding processor.