Electroencephalography (EEG)-based emotion recognition holds significant potential in affective brain-computer interfaces. However, substantial inter-subject variability-due to differences in skull anatomy, electrode placement, and emotional responses-leads to severe spatiotemporal distribution shifts, thus affects the model generalizability. To address this issue, this paper proposes a hypercomplex neural network model based on quaternion rotation, termed Q-RoFormer, which explicitly addresses cross-subject spatiotemporal distribution shifts from both spatial and temporal perspectives. Specifically, the quaternion Transformer module embeds multi-temporal-window EEG segments into a unified quaternion representation, leverages inter-window correlations in quaternion space to mitigate temporal distribution shifts, and applies quaternion rotation to align spatial distribution shifts across subjects. Subsequently, the quaternion long short-term memory network captures temporal dependencies across windows within the quaternion-valued sequence. Furthermore, Q-RoFormer adopts a pre-training-fine-tuning paradigm to enhance transfer learning capabilities. Extensive experiments on the SEED and SEED-IV datasets demonstrate the effectiveness of Q-RoFormer, achieving 93.47% and 81.92% accuracy, respectively. Ablation results confirm the role of spatial rotation in cross-subject generalization.

Physical Unclonable Function (PUF) can be used for device authentication and key generation, leveraging the unique characteristics inherent to individual devices. Collecting multiple Challenge Response Pairs (CRPs) of PUF enable an attacker to conduct a modeling attack. If an attacker snoops on the authentication conversation between the server and the device, PUF is vulnerable to this type of attack. The security solutions that have been proposed based on PUF authentication are considered secure, but they often have a large hardware overhead, making them unsuitable for embedding in resource-constrained devices. In this paper, a lightweight and reliable PUF-based authentication scheme is proposed to protect sensitive CRP data, which uses a nonlinear feedback shift register (NLFSR) to obfuscate the original response to prevent attackers from collecting CRP in open channel to model PUF. The proposed scheme is demonstrated to be effectively resistant to various attacks, including brute force, impersonation, and replay. The prototype of this scheme has been implemented on the Artix-7 FPGA, with a PC serving as the server. The proposed scheme provides a search space and security level that are almost identical to symmetric cipher. Compared to the related work, the average LUT and FF required were decreased by $\mathbf{5 3 \%}$ and $\mathbf{7 5 \%}$, respectively.

This paper proposes an on-chip time-to-digital converter (TDC) named pulse delay and capture circuit (PDCC), dedicated to single-event transient (SET) pulse measurement for radiation characterization of flash-based FPGAs. To address the inherent trade-offs of mainstream vernier delay line (VDL) and snapshot TDC schemes, the proposed PDCC employs a 16-stage single-chain self-triggering capture circuit with a SET indicator flip-flop, incorporates heterogeneous-cell ring-oscillator-based process-voltage-temperature (PVT) calibration, and avoids the need for resource-intensive first-in-first-out (FIFO) buffers. Implemented on a 130 nm A3PE600 flash-based FPGA, the PDCC achieves a nominal theoretical resolution of 640 ps and a nominal theoretical dynamic range of 0.64–10.24 ns, with 53.5% lower logic resource overhead than the VDL benchmark. Heavy-ion irradiation experiments validate the measurement capability and reveal asymmetric SET pulse propagation evolution characterized by positive-pulse broadening and negative-pulse attenuation, as well as sensitivity disparities among logic gates, which are attributed to the physical implementation of internal transistor networks within the VersaTile. A multi-criteria assessment based on the Simple Additive Weighting (SAW) method, evaluating resolution, dynamic range, logic resource overhead, and measured SET pulse width, yields an overall performance score (OPS) of 1.43, corresponding to a 43% higher score relative to the VDL baseline.

Spiking neural networks (SNNs) have been widely applied in image recognition, object detection, and related tasks. However, deploying SNNs on resource-constrained edge devices remains challenging due to their computational complexity and high energy demands. Field-programmable gate arrays (FPGAs) offer a suitable platform for SNN acceleration because of their performance, power efficiency, and flexibility. In this work, we present a novel hardware-oriented SNN accelerator. The leaky integrate-and-fire (LIF) neuron model is optimized by converting it into a discrete-time iterative form, replacing multiply-accumulate (MAC) operations with addition, and combining it with a fixed uniform spike-encoding scheme to reduce resource usage and power consumption. A multidimensional parallel computing array fuses convolution with spike generation and employs a four-stage pipeline to enhance throughput. Max pooling is implemented using OR logic instead of comparators, exploiting the 1-bit spike representation. The accelerator is deployed on a Xilinx XCZU7EV device and operates at 150 MHz, achieving 99.18% accuracy on MNIST, with a latency of 0.46 ms/image and energy consumption of 1.69 mJ/image.

The reconfigurability of IEEE 1687 (IJTAG) enhances test flexibility but also exposes scan paths to security threats such as data sniffing, tampering, and unauthorized access. To mitigate these risks, this paper presents a two-tier secure IJTAG architecture that combines dynamic priority arbitration with a parallel CRC (Cyclic Redundancy Check)-protected scan core. The arbitration module restricts scan participation to instruments with valid configuration bits and priority tokens, providing fine-grained access control. However, while effective against unauthorized access and path manipulation, it cannot detect data tampering. To address this, lightweight checksums are appended at scan-in and verified at scan-out to detect data modifications. Together, these mechanisms block a wider range of attacks and ensure end-to-end scan data integrity. Simulations show that the architecture effectively prevents attacks such as data sniffing and tampering, even when malicious instruments are embedded within the scan path. When implemented in 65 nm CMOS technology, the design incurs less than 35% area overhead, offering robust security with minimal impact on IJTAG compatibility and performance.

Electroencephalogram (EEG), which uses electrodes as highly sensitive sensors to capture the brain's electrical activity, is used to study depression. With the development of graph neural networks (GNNs), topological analysis based on high-density electrodes has become an important research direction in depression detection. However, effective capture of complex spatial relationships between electrodes, particularly long-range dependencies across brain regions, remains challenging. In this work, we propose a method called GNMixer, which enhances the capability of topology representation learning through a local and global information interaction strategy. Specifically, we divide the entire cerebral cortex into multiple subbrain regions, which are considered distinct patches. Inside each patch, we develop a brain patch encoder based on P(2)GNN to enhance the attention of local features. During the encoding process, we employ a precomputed approach to extract multichannel topological features. Outside the patches, we use the multilayer perceptron (MLP)-Mixer to capture interactions between brain regions and explore macroscopic connectivity patterns. In the mental-disorder analysis (MODMA) dataset, the accuracy of GNMixer reaches 93.12%. Our method promotes the advancement of high-density EEG sensor technology in depression detection.

Space radiation-induced Single Event Effects (SEEs) pose a significant threat to circuit reliability, primarily because soft errors—such as Single Event Upsets (SEUs)—possess low energy thresholds and high probabilities of occurrence. To address this, this paper proposes an automated Register Transfer Level (RTL) SEE evaluation method. This approach facilitates the precise generation of faulty and reference circuits while enhancing the controllability and efficiency of SEU injection. The method is validated using a SHA-256 hash circuit containing 1,617 flip-flops, implemented in a TSMC 28nm process. A total of 1.73 million fault injection experiments were conducted. Experimental results indicate a total SEU error rate of 52.18%, comprising 449,741 Failure cases, 323,415 Silent cases, and 88,705 Latent cases. These findings demonstrate that the platform can efficiently evaluate the SEE sensitivity of large-scale circuits, providing robust support for the optimization of radiation-hardened designs.

To enhance the fault tolerance of the fast fourier transform (FFT) processor in the presence of single event effect (SEE), this paper proposes a multistage scalable reduced precision redundancy (MS-RPR) FFT processor. In the MS-RPR FFT, reduced precision redundancy (RPR) is applied to each computational stage, and an adjustable precision design is employed for each reduced precision (RP) module. To compensate for truncation errors in the RP module, both the RPR butterfly units and RPR multiplier units are enhanced. Additionally, the traditional threshold-based voter is optimized to a TMR voter, thereby reducing resource overhead. A fault injection verification scheme is developed via Modelsim and Matlab, and a fault injection scheme is implemented in Python. For comparison, several existing fault-tolerant techniques are implemented on the same benchmark design, using Virtex-7 xc7vx485 FPGA with the operating frequency of 100 MHz. Compared to the average results of existing designs, MS-RPR FFT achieves 49.24% improvement in peak signal-to-noise ratio (PSNR) and 46.42% improvement in PSNR-to-power and slice ratio (PPSR), at the cost of an additional 2.24% resource cost and 2.89% power consumption.

As Convolutional Neural Networks (CNNs) continue to grow in scale, their large number of parameters increasingly constrains training on edge devices. Therefore, quantization algorithms have attracted significant research attention as a method to reduce memory resources. To further overcome the limitations in throughput and resource of existing quantization algorithms, this paper presents a hardware-friendly 16-bit fixed-point (Fix16) quantization training algorithm. By reducing the numerical bit-width, the algorithm lowers hardware resource consumption, which allows more operations to be executed under the same resource. This increases parallelism and consequently leads to higher throughput. Firstly, we design a fixed-point quantizer capable of converting floating-point data into fixed-point. Moreover, to further integrate the quantizer into CNN training, we design a quantization training scheme based on the computational characteristics of each training stage. Experimental results demonstrate that, compared with full-precision and integer quantization algorithms, the proposed algorithm reduces training loss by up to 7.65% and improves accuracy by up to 0.80%. Meanwhile, hardware measurements show that the proposed algorithm reduces power consumption by 50.30%, achieves a throughput of 182.15 GOPS, and improves energy efficiency by $1.44 \times$ compared to the baseline.

Chiplet integration removes the yield and cost barriers of large monolithic SoCs, but it shifts the performance bottleneck to inter-chiplet communication. Conventional die-to-die (D2D) links offer only point-to-point transfers and are poorly suited to modern HPC/AI workloads, which issue frequent data synchronization (broadcast, gather, all-reduce). To solve this challenge, we present a scalable IO Die that turns the point-to-pint interconnection to centralized IO network. This IO die embeds a virtual-channel router with a collective-aware scheduler and reorder buffer enforces deadlock-free context exchange. Additionally, it integrates a lightweight In-Situ Data Processing Engine (IDPE) for on-the-fly vector arithmetic and reduction. These two techniques eliminate repetitive D2D data transfers and satisfy the requirement for dedicated collective communication hardware accelerator in multi-chiplet system. Tested in a 32-chiplet system for LLAMA-70B training task, the prototype in 28 nm CMOS achieves an average throughput of 1.8Tb/s at 500MHz with a burst length of 256, resulting in only 13% lantency overhead within the training process. The IO die reduces data synchronization overhead by up to 86% compared to prior point-to-point interconnect designs.

As the CMOS technology enters nanometer scales, integrated circuits (ICs) become increasingly sensitive to radiation-induced soft errors, which can corrupt the state of storage elements and cause severe reliability issues. Many hardened designs have been proposed to mitigate soft errors by using filtering elements. However, existing filtering elements only protect their inputs against soft errors and leave their outputs unprotected. Therefore, additional filtering elements must be added to protect outputs, resulting in extra overhead. In this paper, we first propose a novel Output-Split C-element (OSC) to protect both its input and output nodes, and then a novel LOw-COst single-node-upset (SNU) self-resilient latch (LOCO) to use OSCs to achieve both soft error resilience and low overhead. The usage of OSCs effectively reduce the short-circuit current of the LOCO latch during switching activities. Furthermore, the usage of clock gating and high-speed path reduces power consumption and delay, respectively. Compared with state-of-the-art SNU-resilient hardened designs, the LOCO latch achieves 19% fewer transistors, 63.58% lower power, 74% less delay, and 92% lower power-delay-product (PDP) on average. In addition, the LOCO latch exhibits better stability under variations in PVT (Process, Voltage, and Temperature).

Due to the gradual reduction in the feature size of transistors in integrated circuits (ICs), triple-node-upsets (TNUs) caused by the striking of energetic particles in harsh radiation environments have become a considerable reliability concern for ICs. To overcome the limitations of current radiation-hardened designs regarding overhead and reliability, this paper proposes a high-performance, low-area-overhead, and low-delay TNU selfrecoverable latch (HLLT) based on N-type stacked transistors for aerospace applications. The proposed HLLT latch comprises three symmetrical modules that protect each other. In addition, high-speed path and clock gating technology are employed to reduce delay overhead and power consumption, respectively. Simulation results show that, compared to five existing TNU-recoverable latches, the proposed HLLT latch achieves average reductions of 29.97 %, 57.12 %, 36.52 %, and 83.00 % in area overhead, power consumption, delay, and areapower-delay-product (APDP), respectively. Furthermore, the proposed HLLT latch has lower sensitivity and better stability to variations in PVT (Process, Voltage, Temperature).

Direct Digital Synthesis (DDS) has become a key technique in modern frequency synthesizers due to its fine frequency resolution, fast switching capability, and digital configurability. Existing lookup-table-based approaches, however, suffer from significant memory footprint and power consumption as the phase-to-amplitude converter (PAC) scales. This paper presents a high-speed DDS architecture tailored for the performance evaluation of high-speed digital-to-Analog converters (DACs). The proposed design employs a quadratic-function-based PAC with quarter-wave symmetry to reduce coefficient storage, while a 16-channel parallel DDS structure enables a 16 × sampling-rate boost. Each sub-DDS operates at 1 GHz with 12-bit amplitude resolution, and an analog multiplexer produces an effective 16 GHz output sampling rate. The design achieves an SFDR above 90 dB, meeting the requirements of DAC linearity and spectral-purity evaluation. Two DDS cores can be combined to generate two-tone test signals for DAC intermodulation testing. Simulation and implementation results demonstrate the feasibility and efficiency of the proposed architecture.

With the continuous evolution of ultra-high-speed time-interleaved chips, the intelligence and reliability of chip testing have become increasingly critical. This paper presents an intelligent test system for an ultra-high-speed time-interleaved ADC chip. The system integrates one-stop operations, including intelligent data acquisition with human intervention, adaptive calibration range selection, and performance index comparison. On the hardware side, a self-developed PCB with high-speed interfaces ensures stable input of sampling signals and clocks, while an FPGA facilitates UART and SPI communication for data upload to a host PC. On the software side, it incorporates COM instrument control and DSP calibration modules to achieve adaptive correction of offset and gain errors. Finally, the system provides a human-machine interface for waveform display and performance analysis, delivering a comprehensive intelligent testing solution.

Aiming at the problem of signal integrity degradation caused by transmission channel loss in high-speed serial links (SerDes) at a data rate of $\mathbf{1 6 ~ G b p s}$, this paper designs a SerDes transmitter (TX) equalizer that complies with the PCIe 4.0 protocol standard. This feed-forward equalizer (FFE) mitigates high-frequency channel attenuation via pre-emphasis techniques and employs a source-series terminated (SST) driver architecture to realize low-noise and low-reflection output characteristics. The circuit design was fully implemented based on a 16 nm FinFET process. Simulation results demonstrate that under the transmission scenario of a transmission line with an equivalent characteristic impedance of 50 ohms, the eye height of the differential output signal of the transmitter reaches 623 mV, the eye width reaches 31.24 ps, and the jitter of 1.09 ps is less than 0.035 UI, which meets the requirements of the PCIe 4.0 protocol; the power consumption test shows that the total power consumption during operation is $\mathbf{3 2 ~ m W}$.

Dynamic analysis and system reliability evaluation are crucial in the design of seismic-resilient reinforced concrete (RC) structures. Uncertainties in earthquake ground motions (EGM) and the spatial variation of heterogeneous concrete must be thoroughly considered. However, implementing these analyses poses significant challenges due to the inherent complexity and high computational costs associated with stochastic nonlinear dynamic analysis and the quantification of concrete’s spatial variation through random field theory. To address these issues, we propose a novel methodology for the stochastic dynamic analysis and system reliability evaluation of RC structures involving spatial variation under stochastic ground motions. In the methodology, a two-scale random field model developed within the framework of stochastic damage mechanics is adopted to capture the coupling effects of the nonlinearity and the spatial variation of concrete. Additionally, a physical-based stochastic ground motion model is utilized to represent the randomness of EGM. Furthermore, the probability density evolution method is employed to derive probabilistic information (statistical moments, and probability density function (PDF), etc.) of dynamic responses, and the system reliability is evaluated by the physical synthesis method. A well-designed five-story RC frame structure is analyzed to demonstrate the efficacy of the proposed methodology and to investigate the influence of concrete’s spatial variation and randomness of EGM on structural responses. The results indicate that the proposed methodology can effectively obtain the probabilistic information of stochastic responses and system reliability, and the concrete’s spatial variation has a non-negligible impact on the structural responses and system reliability.

Depression, a major mental health disorder, has been increasingly prevalent worldwide. The diagnosis of depression through multichannel EEG topology emerges as a promising research direction. So, we introduce a method named MGFormer, designed to explore the complex interactions among channels and unearth underlying patterns within topological structures. Specifically, we propose a channel’s information aggregation strategy. Leveraging the capabilities of graph convolutional networks combined with internal across receptive fields, this approach flexibly extracts the channel’s neighboring features and captures spatial information at varying propagation depths. Compared to traditional GNN-based methods, this mechanism overcomes the limitations of node information aggregation, and pays more attention to the personalized needs of each channel. To optimize this process, we employ a precomputation technique that facilitates the parallel acquisition of these features. Moreover, we develop an information fusion strategy based on the cross-attention Transformer to enhance the dynamic interaction between different modalities. By exchange of query vectors, the model enhances information integration. Our method is verified on the HUSM and MODMA datasets. The model’s accuracy reaches 99.46

Conventional Parallel Decision Feedback Decoder (PDFD) for $\mathbf{1 0 0 0}$ BASE-T transceivers, using Register Exchange Architecture (REA) in the Survivor Memory Unit (SMU), inherently suffers from high dynamic power consumption since the requirement to store and shift symbols for all possible paths at every decoding step, leading to massive register bit-flipping activity. To address this critical inefficiency, this paper leverages path pruning with the $\mathbf{T}$-algorithm to reduce the power consumption in SMU. The core innovation lies in integrating the T-algorithm to discard paths dynamically and deliver the enable signal to the ACSU (Add Compare Select Unit) and SMU. In SMU, these enable signals are used to gate the clock of SMU registers, effectively preventing the storage and unnecessary switching activity associated with pruned paths. These signals are also used in ACSU to eliminate redundant addition operations for discarded paths. Crucially, this power reduction is achieved without effecting BER performance. Synthesized with a 28 nm CMOS standard cell library, the results demonstrate that the proposed decoder achieves a significant 21% reduction in power consumption compared to a conventional PDFD.

In Very Large-Scale Integration(VLSI) circuits deployed in aerospace systems, severe atmospheric radiation induces Single Event Effects(SEEs), where Single Event Upsets(SEUs) trigger transient faults and pose critical reliability challenges. Therefore, AI-assisted prediction of SEU-sensitivity plays a pivotal role in low-overhead hardening of sequential circuits. In this paper, we propose a novel edge-enhanced Graph Attention Network(E2-GAT) model for SEU-sensitive flip-flops(FFs) identification with small-scale fault-injection datasets. By incorporating a Transformer variant, the E2-GAT model effectively integrates circuit topology features into FF-level analysis and expands the receptive field, significantly reducing the dependence on sufficient training samples. Experimental results on the Opencores benchmark demonstrate that E2-GAT achieves an accuracy of 97.05%, a recall of 93.51%, and a ROC AUC of 0.9859 using only 30% of the datasets, while outperforming baselines by average value of 5.22% in accuracy, 6.83% in recall, and 6.25% in ROC AUC.

Convolutional Neural Networks (CNNs) have been widely employed in tasks such as image recognition and object detection. However, the use of CNNs in resource-constrained terminal devices still faces significant challenges, including high computational complexity and excessive energy consumption. Field Programmable Gate Arrays (FPGAs), with their high performance, low power consumption, and flexible configurability, have emerged as an optimal solution for implementation CNN inference accelerators. This paper presents a fixed-point quantization algorithm with adjustable precision. The algorithm optimizes the data flow within the residual network and employs a two-level cache scheme to reduce memory latency. Additionally, loop unrolling and dynamic resource allocation are utilized to improve computational efficiency and enhance hardware resource utilization. In this study, ResNet50 is used as the test model, and the accelerator is validated on the Xilinx ZU49DR platform. The experimental results demonstrate that the proposed accelerator operates at a frequency of 150 MHz, with an average throughput of 696.23 GOPS and a peak throughput of 888.46 GOPS. Its processing speed is 10.67 times faster than That of the Intel i7-12700H CPU platform and 1.26 times faster than that of the NVIDIA GeForce RTX3060 GPU platform. The power consumption is measured at 7.146 W.