This paper presents a research on deployment of neural network model for digit classification on camera captured images on STM32 microcontroller. Translation of model that is based on convolutional neural network uses MNIST dataset for training is presented and evaluated on the example of typical camera consisting embedded systems. Image is captured using OV2640 camera module and real-time inference is performed on STM32H723 microcontroller. Model trained on MNIST dataset. Trained model is compressed to 127.43 KB using X-Cube AI tool. Application of model to the camera captured images led to digit classification, but with significant accuracy drop (from 99.02% during traning to 68% on real-life examples). Results confirm that the model can be ported to resource-constrained devices, but also that real-life application can propose certain limitations.

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This study investigates the effects of irradiation on the performance of carbyne-based surface acoustic wave sensors for ethanol sensing. Carbyne, a carbon allotrope, shows promise in sensing applications, but its stability under radiation, relevant in nuclear and medical settings, is not investigated yet. SAW devices coated with carbyne-enriched films were exposed to 100 kRad of irradiation, and their ethanol-sensing performance was evaluated before and after exposure by measuring impedance, phase angle, resistance, capacitance, and signal response. After irradiation, a slight increase in impedance (approximately 1%) was observed across the frequency range, and the phase angle shifted, with a maximal deviation of approximately 10 degrees. The contact resistance negligibly increased, while the interface capacitance decreased by almost one order of magnitude for some frequencies. Most importantly, the voltage difference between the output and the input signal increased from a 17 mV before irradiation to 172 mV after exposure to 100 kRad, indicating improved sensitivity. Results indicate that irradiation doesn't negatively impact sensor performance; in fact, it enhances sensitivity to ethanol. The study provides insights into the stability of carbyne coatings under harsh conditions and the reliability of carbyne-based SAW sensors following irradiation.

This paper presents an experimental characterization of RADFET sensors. Two irradiation campaigns were carried out at TENMAK (Turkey) and the Vinča Institute (Serbia), employing Co-60 gamma sources with dose rates of $4.813 \mathrm{~Gy} / \mathrm{h}$ and $17.04 \mathrm{~Gy} / \mathrm{h}$, respectively. RADFETs with different gate oxide thicknesses, including dual-gate high-k dielectric structures, were tested by monitoring threshold voltage shifts in response to accumulated radiation dose. The results indicate that devices with thicker oxide layers demonstrate greater sensitivity due to enhanced charge trapping. Moreover, lower dose rates were found to increase sensor sensitivity, particularly in devices with thinner oxides. These findings contribute to the optimization of RADFET design for reliable and accurate total ionizing dose measurements in space environments.

The aim of this study is to develop pMOS dosimeters that can exhibit high performance at high radiation doses compared to traditional SiO2-based RadFETs, for which a dual-gate oxide-layered sensor is proposed. The sensor chips, consisting of two RadFETs of identical thickness and geometry, were fabricated with sensitive region materials of 100 nm and 300 nm thick SiO2, as well as 40 nm HfO2/5 nm SiO2. The threshold voltages (V-th) of the sensors were determined based on voltage values corresponding to 10 mu A ve 50 mu A currents. The initial V-th values at 10 mu A/50 mu A of the RadFETs were -2.89 +/- 0.01 V/-3.84 +/- 0.01 V for 100 nm SiO2, -4.37 +/- 0.02 V/-6.02 +/- 0.02 for 300 nm SiO2, and -1.04 +/-<%0.08 V/-1.507 +/- 0.002 V for HfO2/SiO2. RadFETs were irradiated under a(60)Co radioactive source within a dose range of 1-20 Gy. The sensitivities of the sensors for a cumulative dose of 20 Gy were calculated as 9.19 +/- 0.21/9.81 +/- 0.19 mV/Gy for 100 nm-SiO2-RadFET, 43.72 +/- 0.80/45.94 +/- 0.68 mV/Gy for 100 nm-SiO2-RadFET, and 0.83 +/- 0.01/0.87 +/- 0.02 mV/Gy for DGHK-RadFETs (dual-gate oxide layered with high-k), based on data obtained at 10/50 mu A, respectively. No degradation was observed in any of the sensors during the studied dose range, and the DGHK-RadFETs demonstrated particularly stable behavior. Lower error rates in performance parameters, higher stability, more durable in high radiation environments, greater dose storage capability with the lowest fading values, and the ability to reach saturation at higher doses were observed in DGHK-RadFETs compared to SiO2-RadFETs. All these superior properties compared to traditional structures have been achieved in DGHK-RadFETs with a thinner sensitive region. The DGHK-RadFET prototype is a promising candidate for potential applications in nuclear power plants, space research, high-energy physics laboratories, and defense and security applications.

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This study investigates the effects of NBTI on p-channel Vertical Double-Diffused MOSFETs (VDMOS), focusing on threshold voltage degradation and the potential for recovery through thermal relaxation. Devices were subjected to static NBT stress followed by relaxation at various temperatures. The measured transfer characteristics revealed a shift along the voltage axis, indicating changes in threshold voltage during the early stress phases, followed by saturation over time. High-temperature relaxation induced partial recovery of the degraded parameters, while low-temperature treatments had no significant recovery effect. These findings contribute to a better understanding of degradation and recovery mechanisms in power VDMOS transistors and support the design of more reliable, high-performance electronic systems.

This paper presents a comparison between the efficiency of non-learning and machine learning approaches on edge devices, using a typical NFC system centred around commercial ESP32 microcontroller as an example. NFC tag data is read by the NFC reader and forwarded to two ESP32 modules, one using rule-based non-learning approach, and the other one using pretrained model for text correction. Read success rate as well as self-heating are analyzed on the basis of 100 unsuccessful data processing attempts. Machine learning method shows $4 \%$ better read success rate, but also suffers from more self-heating.

In this paper, the applicability of existing machine learning (ML) models for predicting the variation of Single Event Transient (SET) pulse width during propagation through standard combinational cells is analyzed. Ten regression models have been trained on a dataset generated from SPICE simulations conducted for INV, NAND2 and NOR2 gates from the IHP’s 130 nm standard cell library. The SET pulse width at the output of each gate was analyzed in terms of input pulse width and polarity, size factor of analyzed gate, size factor of load gate, supply voltage and temperature. Results have shown that some models provide best prediction accuracy for specific gates. The trained models could be also used to predict the change of SET pulse width across combinational paths, but the prediction accuracy in that case is lower than for individual gates. Future work will be focused on improving the prediction accuracy of ML models and development of an automated ML-based tool-flow for SET analysis.

In this paper, the impact of negative bias temperature instabilities (NBTIs) on commercial power p-channel Vertical Double-Diffused MOS (VDMOS) transistors from the standpoint of practical applications was analyzed. The effects of NBTI are one of the main reliability concerns for this type of device, so it is necessary to investigate how these effects influence various applications. A series of experiments were carried out including negative bias temperature stressing, infra-red thermographic recording and circuit characterization, with the goal of evaluating the effects of negative bias temperature stressing on the self-heating of samples in load-driving circuits operating with higher currents and circuit performance of a CMOS inverter circuit containing the examined samples. The findings suggest that negative bias temperature stressing-induced threshold voltage shift directly affects increased self-heating in load-driving circuits and that it also directly affects transfer and dynamics characteristics in CMOS inverters.

This paper presents an experimental and SPICE-based modeling approach for analyzing NBTI (Negative Bias Temperature Instability) and SHE (Self-Heating Effects) in power p-channel VDMOS transistors IRF9520. The objective is to enhance existing models and enable accurate prediction of device behavior under prolonged electrical and thermal stress, as well as during the recovery (relaxation) phase. Experiments were performed by applying a gate stress of - 45 V at 175 degrees C for 96 hours, followed by relaxation at multiple temperatures ranging from - 40 degrees C to 175 degrees C, based on which the degradation models were developed. Voltage shift data were fitted using power-law and exponential-law expressions, and implemented in SPICE for long-term performance estimation. Additionally, self-heating effects were characterized using thermal imaging under different signal shapes and current levels, and modeled using equivalent RC networks. The proposed models show good agreement with experimental data and can be used to predict degradation trends in power PMOS transistors for reliability-aware circuit design.

This paper presents a performance analysis of three digital multiplier architectures—array, Wallace without carry-look-ahead (CLA), and Wallace with CLA logic—targeted for neural network (NN) accelerators. Simulations were performed using an IHP's 130 nm CMOS standard cell library in Cadence Spectre, focusing on propagation delay and power consumption across different supply voltages, temperatures and transistor dimensions. The Power Delay Product (PDP) was used to evaluate overall efficiency. Results show that the Wallace multiplier without CLA logic and the smallest cells offers the best trade-off in terms of delay and power, making it a strong candidate for low-power, high-performance applications.

This work focuses on analyzing the influence of thermal relaxation following prolonged NBTS (Negative Bias Temperature Stress). The experimental setup features a CMOS inverter composed of a p-channel IRF9520 and a n-channel IRF510 transistor, with dynamic characteristics evaluated over a wide temperature range from -40 degrees C to +180 degrees C. Comparison between the characteristics of a CMOS inverter consisting of a non-stressed and stressed PMOS devices is given. PMOS samples were divided into three groups. All of the groups were subjected to the NBT stressing, after which the first group was subjected to thermal relaxation at 175 degrees C, the second one at 25 degrees C and the third one at - 25 degrees C. Threshold voltage value was monitored during the NBT stress and thermal relaxation. The results demonstrate a clear correlation between temperature, threshold voltage shifts, and CMOS inverter switching times. The highest thermal relaxation temperature (175 degrees C) partially mitigates the NBTS induced PMOS threshold voltage shift, leading to faster inverter response. This study emphasizes the importance of accounting for both aging and recovery phenomena when analyzing the dynamic performance of CMOS circuits, especially in applications exposed to elevated or negative temperatures and extended operation.

We report on a procedure for extracting the SPICE model parameters of a RADFET sensor with a dielectric HfO2/SiO2 double-layer. RADFETs, traditionally fabricated as PMOS transistors with SiO2, are enhanced by incorporating high-k dielectric materials such as HfO2 to reduce oxide thickness in modern radiation sensors. The fabrication steps of the sensor are outlined, and model parameters, including the threshold voltage and transconductance, are extracted based on experimental data. Experimental setups for measuring electrical characteristics and irradiation are described, and a method for determining model parameters dependent on the accumulated dose is provided. A SPICE model card is proposed, including parameters for two dielectric thicknesses: (30/10) nm and (40/5) nm. The sensitivities of the sensors are 1.685 mV/Gy and 0.78 mV/Gy, respectively. The model is calibrated for doses up to 20 Gy, and good agreement between experimental and simulation results validates the proposed model.

This study investigates the effects of negative bias temperature (NBT) stress and irradiation on the threshold voltage (VT) of p-channel VDMOS transistors, focusing on degradation, recovery after each type of stress, and operational behavior under varying conditions. Shifts in VT (ΔVT) were analyzed under different stress orders, showing distinct influence mechanisms, including defects creation and their removal and electrochemical reactions. Recovery data after each type of stress indicated ongoing electrochemical processes, influencing subsequent stress responses. Although the ΔVT is not particularly pronounced during the recovery after irradiation, changes in subthreshold characteristics indicate the changes in defect densities that affect the behavior of the components during further application. Additionally, the findings show that the ΔVT during the NBT stress after irradiation (up to certain doses and conditions) remains relatively stable, but this is the result of a balance of competing mechanisms. A subthreshold characteristic analysis provided a further insight into the degradation dynamics. A particular attention was paid to analyzing ΔVT with a focus on predicting the lifetime. In practical applications, especially under pulsed operation, prior stresses altered the device’s thermal and electrical performance. It was shown that self-heating effects were more pronounced in pre-stressed components, increasing the power dissipation and thermal instability. These insights additionally highlight the importance of understanding stress-induced degradation and recovery mechanisms for optimizing VDMOS transistor reliability in advanced electronic systems.

This paper describes a modified SPICE-compatible VDMOS transistor model that includes NBT and self-heating effects. A complete circuit diagram of the transistor is given, which includes the electrical part of the circuit that models the NBT effect and the equivalent thermal part of the circuit that models the self-heating effect. The parameters of the model were determined based on the technical documentation and the fitting method based on the performed experiments. Fresh transistors and NBT-stressed transistors, with and without a heatsink in the load-driving circuit, were considered. The results of experiments and simulations correspond to each other with a maximum deviation of up to 10%. The proposed model can be used in the design and analysis of transistor reliability parameters.

U ovom radu vršeno je ispitivanje specifične električne otpornosti i PTC efekta (izražen Pozitivno Temperaturni Koeficijent) kod BaTiO3 keramike, dopirane različitim aditivima. Za dopiranje barijum titanatne keramike korišćeni su joni retkih zemalja Yb3+ i Ho3+ u koncentracijama od 0.01 at% do 1.0 at%. Ispitivani uzorci su dobijeni primenom konvencionalne metode u čvrstom stanju i sinterovani na temperaturi 1320°C. Na nižim koncentracijama, kod uzoraka dopiranih Yb veličina zrna bila je u opsegu od 10 μm do 40 μm, dok se kod uzoraka dopiranih Ho kretala od 10 μm do 30 μm. Za niže koncentracije karakterističan je abnormalni rast zrna. Sa povećanjem koncentracije, veličina zrna je opadala, tako da se na najvišoj koncentraciji 1.0 at%, kretala od 1 μm do 10 μm. Specifična električna otpornost je merena u temperaturnom intervalu od 30°C do 170°C i u frekventnom opsegu od 1 kHz do 1 MHz. Porast temperature uticao je na promene vrednosti specifične električne otpornosti i njen porast. Za vrednost specifične električne otpornosti je karakteristična neznatna promena u intervalu od sobne temperature do 100°C, nakon čega dolazi do nagle promene vrednosti. Povećanjem frekvencije zabeležen je pad vrednosti specifične električne otpornosti za nekoliko reda veličine.

This study investigates the reliability and performance of p-channel power VDMOS transistors subjected to different stresses NBT, PBT, HEF, and irradiation. Results reveal distinct degradation patterns in electrical parameters, with threshold voltage shifts particularly affected. Notably, positive HEF stress can produce a „turn-around“ effect in investigated devices. Also, irradiated devices show degradation trends similar to those under HEF stress, emphasizing the influence of ionizing radiation on stability. Additionally, self-heating effects in stressed devices highlight vulnerability under real operating conditions. These findings are crucial for enhancing the reliability of VDMOS transistors in high-stakes applications such as automotive, aerospace, and high-reliability switching circuits.

This study aimed to comprehensively understand the performance and degradation of both p- and n-channel vertical double diffused MOS (VDMOS) transistors under bias temperature stress. Conducted experimental investigations involved various stress conditions and annealing processes to analyze the impacts of BT stress on the formation of oxide trapped charge and interface traps, leading to threshold voltage shifts. Findings revealed meaningful threshold voltage shifts in both PMOS and NMOS devices due to stresses, and the subsequent annealing process was analyzed in detail. The study also examined the influence of stress history on self-heating behavior under real operating conditions. Additionally, the study elucidated the complex correlation between stress-induced degradation and device reliability. The insights contribute to optimizing the performance and permanence of VDMOS transistors in practical applications, advancing semiconductor technology. This study underscored the importance of considering stress-induced effects on device reliability and performance in the design and application of VDMOS transistors.