Hardware implementations of the Ising model offer promising solutions to large-scale optimization tasks. In the literature, various nanodevices have been shown to emulate the spin dynamics for such Ising machines with remarkable effectiveness. Other nanodevices have been shown to implement spin-spin coupling with compact footprint and minimal energy dissipation. However, an ideal Ising machine would associate both types of nanodevices, and they must operate synergistically to support annealing: a progressive reduction of machine stochasticity that allows it to settle to an energy minimum. Here, we report an Ising machine that combines two nanotechnologies: memristor crossbar - storing multi-level couplings - and stochastic magnetic tunnel junction (SMTJ), acting as thermally driven spins. Because the same read voltage that interrogates the crossbar also biases the SMTJs, increasing this voltage automatically lowers the effective temperature of the machine, providing an intrinsic, analog-native annealing technique. Operating at zero magnetic field, our prototype consistently reaches the global optimum of a 24-vertex weighted MAX-CUT and a 10-vertex, three-color graph-coloring problem using an externally implemented feedback loop. Given that both nanotechnologies in our demonstrator are CMOS-integrated, this approach is compatible with advanced 3D integration, offering a scalable pathway toward compact, fast, and energy-efficient large-scale Ising solvers.

Always-on edge systems must keep learning as conditions change under tight compute budgets and must detect unreliable predictions. Bayesian binary neural networks are attractive in this setting, but mean-field Bernoulli posteriors can saturate on long non-stationary streams, wiping out epistemic uncertainty and freezing plasticity. We propose BiMU, derived from a bounded-memory variational objective that balances stability, plasticity, and forgetting. BiMU combines a data term with controlled relaxation toward the prior and an uncertainty-dependent step size that prevents saturation and sustains informative uncertainty. This non-degenerate posterior enables fully online, buffer-free active querying via Monte Carlo disagreement, reducing label queries and backpropagation updates under imbalance. BiMU sustains learning and strong OOD detection on 1000-task Permuted-MNIST, and on OpenLORIS-Object achieves up to 32× label/update savings at matched accuracy under class imbalance and feature compression.

The deployment of AI on edge computing devices faces significant challenges related to energy consumption and functionality. These devices could greatly benefit from brain-inspired learning mechanisms, allowing for real-time adaptation while using low-power. In-memory computing with nanoscale resistive memories may play a crucial role in enabling the execution of AI workloads on these edge devices. In this study, we introduce voltage-dependent synaptic plasticity (VDSP) as an efficient approach for unsupervised and local learning in memristive synapses based on Hebbian principles. This method enables online learning without requiring complex pulse-shaping circuits typically necessary for spike-timing-dependent plasticity (STDP). We show how VDSP can be advantageously adapted to three types of memristive devices (TiO2, HfO2-based metal-oxide filamentary synapses, and HfZrO4-based ferroelectric tunnel junctions (FTJ)) with disctinctive switching characteristics. System-level simulations of spiking neural networks incorporating these devices were conducted to validate unsupervised learning on MNIST-based pattern recognition tasks, achieving state-of-the-art performance. The results demonstrated over 83

Turning memristor arrays from efficient inference engines into systems capable of on-chip learning has proved difficult. Weight updates have a high energy cost and cause device wear, analog states drift, and backpropagation requires a backward pass with reversed signal flow. Here we experimentally demonstrate learning on standard filamentary HfOx/Ti arrays that addresses these challenges with two design choices. First, we realize that standard filamentary HfOx/Ti memristors support sub-1 V reset-only pulses that cut energy, improve endurance, and yield stable analog states. Second, we rely on forward-only training algorithms derived from Hinton's Forward-Forward that use only inference-style operations. We train two-layer classifiers on an ImageNet-resolution four-class task using arrays up to 8,064 devices. Two forward-only variants, the double-pass supervised Forward-Forward and a single-pass competitive rule, achieve test accuracies of 89.5

Memristors have been intensely investigated for memory applications and neural network accelerators. In this Comment, we discuss the requirements for how memristor technologies should evolve for Bayesian in-memory computing.

Memristor computing offers a route to low-energy edge AI, but device variability, sensitivity to operating conditions, and system-integration challenges can hinder deployment. Here we show that these limitations can be mitigated by using memristor AI not as the final decision maker but as the ultra-low-power, always-on front end of a heterogeneous inference system. We implement this architecture by coupling a fabricated memristor Bayesian machine to a programmable CPU running a higher-power, higher-accuracy software neural network. The memristor front end acts as a probabilistic screener. When it predicts an abnormal event or produces an ambiguous or invalid output, a dedicated hardware wake-up path activates the CPU, which produces the final decision. We validate this architecture on a heartbeat-classification benchmark by interfacing the fabricated Bayesian machine with an FPGA-based wake-up platform and CPU back end. The resulting uncertainty-triggered wake-up system achieves high final classification accuracy under nominal operation and maintains this accuracy even when the memristor front end is degraded by voltage scaling or reduced programming margins, because unreliable outputs are converted into recoverable wake-up events instead of becoming silent errors. Post-layout analysis of an ASIC implementation shows that average energy is governed primarily by wake-up frequency, providing practical design rules for choosing front-end operating points. These results establish uncertainty-triggered wake-up as a strategy for energy-efficient, error-resilient edge AI.

By combining several probabilistic AI algorithms, a recent study demonstrates experimentally that the inherent noise and variation in memristor nanodevices can be exploited as features for energy-efficient on-chip learning.

Artificial intelligence (AI) increasingly powers safety-critical systems that demand robust, energy-efficient computation, often under conditions of data scarcity and uncertainty. Traditional AI approaches are limited in their ability to quantify confidence, leaving them vulnerable to unreliable predictions. In this Perspective, we introduce Bayesian electronics, which harnesses the intrinsic randomness of emerging nanodevices for on-device Bayesian computations. By encoding probability distributions at the hardware level, these devices naturally estimate uncertainty and reduce overhead compared with purely deterministic designs. We examine how Bayesian networks and Bayesian neural networks can be implemented in this framework to enhance sensor fusion and out-of-distribution detection. We also describe how hardware training via Markov chain Monte Carlo or Langevin dynamics yields energy-frugal sampling-based learning. Finally, we draw parallels with biological systems that are hypothesized to similarly exploit noise for probabilistic computation. By integrating device engineering, algorithmic design and system-level optimization, Bayesian electronics offers a path towards more trustworthy and adaptive AI hardware. Bayesian electronics harness the randomness of noisy sensor data to quantify uncertainty and make predictions at low computational cost. This Perspective shows how they can be realized to improve reliability and reduce energy in wearable devices, smart industrial sensors and autonomous robots

The ever-increasing amount of data from ubiquitous smart devices fosters data-centric and cognitive algorithms. Traditional digital computer systems have separate logic and memory units, resulting in a huge delay and energy cost for implementing these algorithms. Memristors are programmable resistors with a memory, providing a paradigm-shifting approach towards creating intelligent hardware systems to handle data-centric tasks. Spintronic nanodevices are promising choices as they are high-speed, low-power, highly scalable, robust, and capable of constructing dynamic complex systems. In this Review, we survey spintronic devices from a memristor point of view. We introduce spintronic memristors based on magnetic tunnel junctions, nanomagnet ensemble, domain walls, topological spin textures, and spin waves, which represent dramatically different state spaces. They can exhibit steady, oscillatory, stochastic, and chaotic trajectories in their state spaces, which have been exploited for in-memory logic, neuromorphic computing, stochastic and chaos computing. Finally, we discuss challenges and trends in realizing large-scale spintronic memristive systems for practical applications.

Biological synapses effortlessly balance memory retention and flexibility, yet artificial neural networks still struggle with the extremes of catastrophic forgetting and catastrophic remembering. Here, we introduce Metaplasticity from Synaptic Uncertainty (MESU), a Bayesian update rule that scales each parameter's learning by its uncertainty, enabling a principled combination of learning and forgetting without explicit task boundaries. MESU also provides epistemic uncertainty estimates for robust out-of-distribution detection; the main computational cost is weight sampling to compute predictive statistics. Across image-classification benchmarks, MESU mitigates forgetting while maintaining plasticity. On 200 sequential Permuted-MNIST tasks, it surpasses established synaptic-consolidation methods in final accuracy, ability to learn late tasks, and out-of-distribution data detection. In task-incremental CIFAR-100, MESU consistently outperforms conventional training techniques due to its boundary-free streaming formulation. Theoretically, MESU connects metaplasticity, Bayesian inference, and Hessian-based regularization. Together, these results provide a biologically inspired route to robust, perpetual learning.

Developing artificial intelligence systems that are capable of learning at the edge of a network requires both energy-efficient inference and learning. However, current memory technology cannot provide the necessary combination of high endurance, low programming energy and non-destructive read processes. Here we report a unified memory stack that functions as a memristor as well as a ferroelectric capacitor. Memristors are ideal for inference but have limited endurance and high programming energy; ferroelectric capacitors are ideal for learning, but their destructive read process makes them unsuitable for inference. Our memory stack uses a silicon-doped hafnium oxide and titanium scavenging layer that are integrated into the back end of line of a complementary metal–oxide–semiconductor process. With this approach, we fabricate an 18,432-device hybrid array (consisting of 16,384 ferroelectric capacitors and 2,048 memristors) with on-chip complementary metal–oxide–semiconductor periphery circuits. Each weight is associated with an analogue value stored as conductance levels in the memristors and a high-precision hidden value stored as a signed integer in the ferroelectric capacitors. Weight transfers between the different memory technologies occur without a formal digital-to-analogue converter. We use the array to validate an on-chip learning solution that, without batching, performs competitively with floating-point-precision software models across several benchmarks. A memory technology that combines the functions of memristors and ferroelectric capacitors in a single stack can be used for on-chip training and inference of artificial neural networks.

The demand for explainable and energy-efficient artificial intelligence (AI) systems for edge computing has led to growing interest in electronic systems dedicated to Bayesian inference. Traditional designs of such systems often rely on stochastic computing, which offers high energy efficiency but suffers from latency issues and struggles with low-probability values. Here, we introduce the logarithmic memristor-based Bayesian machine, an innovative design that leverages the unique properties of memristors and logarithmic computing as an alternative to stochastic computing. We present a prototype machine fabricated in a hybrid CMOS/hafnium-oxide memristor process. We validate the versatility and robustness of our system through experimental validation and extensive simulations in two distinct applications: gesture recognition and sleep stage classification. The logarithmic approach simplifies the computational model by converting multiplications into additions and enhances the handling of low-probability events, which are crucial in time-dependent tasks. Our results demonstrate that the logarithmic Bayesian machine achieves superior performance in terms of accuracy and energy efficiency compared to its stochastic counterpart, particularly in scenarios involving complex probabilistic models. This approach enables the development of energy-efficient and reliable AI systems for edge devices. Clement Turck and colleagues present an alternative computing platform leveraging the property of logarithm to transfer multiplication operation into addition. They demonstrate the energy efficiency and superior performance of the prototype on gesture recognition and sleep stage recognition benchmark tasks.

Multifunctional hardware technologies for neuromorphic computing are essential for replicating the complexity of biological neural systems, thereby improving the performance of artificial synapses and neurons. Integrating ionic and spintronic technologies offers new degrees of freedom to modulate synaptic potentiation and depression, introducing novel magnetic functionalities alongside the established ionic analogue behavior. We demonstrate that magneto-ionic devices can perform as synaptic elements with dynamically tunable depression linearity controlled by an external magnetic field, a functionality reminiscent of neuromodulation in biological systems. By applying magnetic fields we significantly reduce the nonlinearity of synaptic depression, transitioning from an exponential dependence to a linear response at higher fields. Neural network simulations reveal that this magnetically induced linearity enhancement improves learning accuracy across a wide range of learning rates, which is retained after the magnetic field is removed. These findings highlight the versatility and promise of magneto-ionic devices for developing tunable synaptic elements for neuromorphic hardware.

A key challenge that traditional ML methods suffer from is catastrophic forgetting, a phenomenon in which the model overwrites previously learned knowledge to learn new tasks. The field of continual learning aims to develop machine learning (ML) models capable of adapting to additional knowledge. Continual learning is essential to enable real-time epileptic seizure detection, which is currently a limiting factor, especially in a resource-constrained environment such as implantable edge devices. Biological metaplasticity has become a topic of interest as an application to these systems. This paper employs metaplasticity in a low-power binarized neural network (BNN) to maintain stable learning when EEG data is streamed into the network. Our model improves on baseline performances from traditional ML architectures. The metaplastic BNN in this paper reports performance metrics of accuracy and ROC-AUC values over 70

Continuous learning of time-series signals and energy-critical systems has received growing attention. Fueled by advances in edge computing and innovative architectures, there is an opportunity to unite these to develop clinically targeted solutions, including epileptic seizure suppression. In implantable devices, wireless data telemetry requires specific bandwidths for brain interfacing. Developing a low-power continual learning system is one promising avenue to address this. These algorithms should adapt to additional knowledge streamed episodically. Biological metaplasticity is a potential technique for longer-term stability during learning. This paper uses this technique in a low-power architecture to develop stable learning on multiple EEG (electroencephalogram) datasets for seizure detection. In this feasibility study, metaplastic synapses enhance detection accuracy relative to baselines. Metaplastic binarized neural networks (BNNs) demonstrate improvement (6–7%) in seizure detection performance, with reported accuracies and ROC-AUCs over 70%. Metaplastic BNNs hold the potential to provide an adaptable, patient-specific seizure-tracking method for real-world dynamics.

Designing algorithms for versatile AI hardware that can learn on the edge using both labeled and unlabeled data is challenging. Deep end-to-end training methods incorporating phases of self-supervised and supervised learning are accurate and adaptable to input data but self-supervised learning requires even more computational and memory resources than supervised learning, too high for current embedded hardware. Conversely, unsupervised layer-by-layer training, such as Hebbian learning, is more compatible with existing hardware but does not integrate well with supervised learning. To address this, we propose a method enabling networks or hardware designed for end-to-end supervised learning to also perform high-performance unsupervised learning by adding two simple elements to the output layer: winner-take-all selectivity and homeostasis regularization. These mechanisms introduce a ‘self-defined target’ for unlabeled data, allowing purely unsupervised training for both fully-connected and convolutional layers using backpropagation or equilibrium propagation on datasets like MNIST (up to 99.2%), Fashion-MNIST (up to 90.3%), and SVHN (up to 81.5%). We extend this method to semi-supervised learning, adjusting targets based on data type, achieving 96.6% accuracy with only 600 labeled MNIST samples in a multi-layer perceptron. Our results show that this approach can effectively enable networks and hardware initially dedicated to supervised learning to also perform unsupervised learning, adapting to varying availability of labeled data.