Many streaming applications feature coarse grain task farm or pipeline parallelism and can be modeled as a set of parallel threads. Performance requirements can often only be met by mapping the application onto a Multi Processor System-on-Chip (MPSoC). To avoid contention, hierarchical interconnection networks, where the central interconnect is a network-on-chip, are employed. In such a clustered MPSoC, the memory access latency varies strongly depending on the location of data, and is the principal cause of out-of-order arrival of data items. We present an algorithm which re-establishes the order of data items on the output side. If their earliness or lateness exceeds a limit previously fixed by experimentation, they are dropped, otherwise stored in a buffer. Write operations to this buffer are random access, whereas read operations are in FIFO order. Our algorithm guarantees that no data is removed from the buffer before it has been read, and, for a given throughput, minimum buffer size. The algorithm was implemented within the output co-processors for three application case studies and validated on a simulation platform based on the SoCLib library.

We consider streaming applications modeled as a set of coarse-grained parallel threads. Their Task and Communication Graph (TCG) can contain pipeline or task farm parallelism, or any combination of both. Applications can be written in the form of several parallel pipelines. Data are potentially read and forwarded in an arbitrary order by a task which joins the streams having passed through the pipelines; such out-of-order arrival is unacceptable in video streaming. Mapping a multi-pipeline TCG on a clustered multi processor system-on-chip, where memory access latency varies strongly, further aggravates the problem. We present several methods to re-establish the order between data items; all these methods use a so-called merge task. This task employs an order re-establishing algorithm which uses a re-ordering buffer, initially described for telecommunication applications. The algorithm discards, on entering the re-ordering buffer, data items arriving too early or too late; it thus guarantees minimal buffer space. Preliminary experimental results are given for a multi-pipeline Motion JPEG decoder.

We consider video streaming applications written in the form of coarse-grained parallel threads which are mapped onto a multi processor system-on-chip. For performance reasons, the threads are replicated, organized into several parallel pipelines, and mapped onto a clustered architecture. This type of architecture has non uniform memory access so that latencies vary strongly. As a consequence, data items potentially arrive at the join task in an arbitrary order, but have to leave in-order. We extend an algorithm initially conceived for networking applications. This algorithm re-establishes the order while using minimal buffer space for a given throughput. Data items are either stored in a buffer or discarded if their earliness or lateness exceeds a limit previously fixed by experimentation. The extended algorithm handles the notion of hierarchy which is typical for video streaming: several blocks make up a stripe, several stripes make up a frame and so forth. We show first experimental results for a multi-pipeline Motion JPEG decoder on a multi-cluster SoC and compare with an existing implementation.

The particular form of the task graph of many telecommunication applications permits a high level of coarse grained parallelism. We consider a classification application on a telecommunication oriented multiprocessor system-on-chip (MP-SoC) platform. The hardware architecture hosting this type of application contains many programmable processors and dedicated hardware coprocessors, sharing the same address space. Inter-task communications are implemented via Multi-Writer Multi-Reader (MWMR) channels placed in shared-memory. To meet the strict requirements of this type of application, several performance bottlenecks have to be overcome. We show how our tool DSX (Design Space Explorer) helps to analyze these bottlenecks and outline the perspectives for further improvement.

We show how to increase locality of object-oriented programs using several heaps. We introduce the notion of sandwich types which allow a coarser view on objects. Our idea for increasing locality is to use one heap per object of sandwich types. Performance measurements demonstrate that the running time is improved by upto a factor 5 using this strategy. The paper shows how to derive sandwich types from classes. Thus, it is possible to control the allocation of the different heaps using compile-time information.

Simulation platforms for network processing still have difficulties in finding a good compromise between speed and accuracy. This makes it difficult to identify the causes of performance bottlenecks: Are they caused by application, hardware architecture, or by a specificity of the operating system? We propose a simulation methodology for a multiprocessor network processing platform which contains sufficient detail to permit very precise simulation and performance evaluation while staying within reasonable limits of both specification and simulation time. As a case study, we show how a model can be developed for a IPv4 packet routing application, exhibiting the performance and scalability bottlenecks and can thus be used to reason about architectural alternatives.

Pervasive video processing in future Ambient Intelligence environments sets new challenges in embedded system design. In particular, very high performance requirements have to be combined with the constraints of deeply embedded systems, frequently changing operating modes, and low-cost, high-volume production. By leveraging upon the key properties of the application domain, we devised a computation model, a hardware template, and a programming approach which provide a natural mapping from application requirements to a complete system solution. Our approach enables the direct exploitation of concurrency and regularity in achieving the combined challenge of adaptability, performance, and efficiency.

This paper aims at modeling video stream applications with structured data and multiple clocks. Multi-Periodic Process Networks (MPPN) are real-time process networks with an adaptable degree of synchronous behavior and a hierarchical structure. MPPN help to describe stream-processing applications and deduce resource requirements such as parallel functional units, throughput and buffer sizes.

In this paper we construct an analytic model of cache misses during matrix multiplication. The analysis in this paper applies to square matrices of size 2m where the array layout function is given in terms of a function Θ that interleaves the bits in the binary expansions of the row and column indices. We first analyze the number of cache misses for direct-mapped caches and then indicate how to extend this analysis to A-way associative caches. The work in this paper accomplishes two things. First, we construct fast algorithms to estimate the number of cache misses. Second, we develop a theoretical understanding of cache misses that will allow us, in subsequent work, to approach the problem of minimizing cache misses by appropriately choosing the bit interleaving function that goes into the array layout function.

Even though there is a growing interest in Java-based embedded computing, compilers have to solve several problems before they can produce high performance Java code. On the one hand, Java's advanced features, e.g. calls of virtual methods, need to be optimized with appropriate inter-class techniques. Additionally, Java 's memory management requires fast garbage collection observing real-time deadlines. On the other hand, new hardware trends create problems: heterogeneous parallel embedded systems require new techniques for performance optimization, and cache storage needs to be allocated by the compiler in order to exploit the speed of new processors. To meet these requirements, the EU long-term research project JOSES (Java and CoSy technol- ogy for Embedded Systems) has been initiated. Its mission is to create a Java-based European technology for heterogeneous embedded systems, including an optimizing Java compiler environment producing high-performance native code. JOSES will ex- ploit the European product-quality compiler framework CoSy, marketed by ACE. This component-based technology allows re-use of existing compiler engines and employs generator technology wherever possible.

Scientific computing and image processing applications access largeamounts of data in regular patterns. In order to relieve the memory bottleneck,caching tries to keep recently referenced data available in fast storage.

Scienti c computing and image processing applications access large amounts of data in regular patterns In order to relieve the memory bottle neck caching tries to keep recently referenced data available in fast storage This is increasingly important as the gap between processor and memory hierarchy speed has widened in recent years There are two main di culties that cannot be dealt with by hardware alone Firstly a cache line usually holds several values often only one of them is actually used Secondly con icting accesses to one cache line cause data to be evicted which is still required In the extreme case data is replaced on every access a situation we denote as cache thrashing To overcome these problems the temporal spatial structure of accesses has to be changed Compile time cache optimizations exploit regular access patterns Loop transformations as e g tiling are well established For caches with limited associativity it is often crucial to additionally adjust the placement of data in memory We show that compiler techniques for register allocation namely graph coloring support a systematic data placement For innermost loops con icts and temporal reuse can be modeled to gether in a cyclic interval graph If reuse stretches over several loop itera tions live ranges may overlap themselves prohibiting usual cyclic coloring By applying the meeting graph method the compiler can determine an un rolling factor and determine the maximal number of colors i e of cache lines required Values of the same color are mapped to memory together Since these values may stem from di erent data structures our technique o ers a nat ural way of dealing with con icts between di erent arrays We implement this scheme through modifying the standard memory mapping At run time the new compile time mapping function is used as index function The tradeo between the additional cost for more complex indexing and reduced miss penalty is re ected by a cost function For typical example codes from the above areas reuse and con ict be havior are considerably improved yielding moderate run time reductions In addition on a more coarse level paging activity is often signi cantly postponed

Algorithms which access memory regularly are typical for scientific computing, image processing and multimedia. Cache conflicts are often responsible for performance degradation, but can be avoided by an adequate placement of data in memory. The huge search space for such compile time placements is systematically reduced until we arrive at a class of very simple mappings, well known from data distribution onto processors in parallel computing. The choice of parameters is then guided by a cost function which reflects the tradeoff between additional instruction overhead and reduced miss penalty. We show by experiment that when keeping the overhead low, a considerable speedup can be achieved.

We show that cyclic graph coloring techniques from loop register allocation are successfully applicable to caches. Values of one color belong together, even if they stem from different data structures, resulting in a sytematic merging.