Log-structured merge-tree (LSM-tree) key-value stores rely on caching to mitigate multi-component lookups and long tails, yet block and KP caches are prone to compactioninduced expiry, and all three cache types suffer from scan pollution under LRU eviction. We present AutoThermKV, a two-level in-memory architecture that decouples fast admission from hot-item protection. The front tier (HotFilter) uses a 64 Baligned bitmap/key/value page layout with Quick Space Reservation for near-constant admission cost; the back tier (HotCommitted) retains proven hot items via a lightweight LRU and a secondtouch promotion rule. Implemented atop RocksDB and evaluated on YCSB-like workloads with controllable temporal locality, AutoThermKV achieves up to 2.58 × throughput speedup, 2.60 × average-latency reduction, and tail-latency improvements of up to 20 × (p99) and 36 (p999) under modest memory budgets.

Full‐state quantum circuit simulators play a significant role in the design and validation of quantum algorithms. With an increasing demand for the number of quantum bits (qubits), achieving efficient simulations under memory constraints emerges as a technical challenge since a state vector with elements should be maintained in each simulation step, where denotes the number of qubits. Previous work, CompQSim, partitions a state vector into blocks and uses block compression to conduct larger‐scale in‐memory simulations on supercomputers. Since the effectiveness of compressors depends on the distinctive characteristics exhibited by the circuits during simulations, an adaptive algorithm is designed to employ data compression and secondary storage astutely. The costs associated with the block processing, including the (de)compression and I/O, constitute a major portion of simulation time. To minimize such costs, two novel simulation algorithms, called BlkQSim and HyQSim are proposed. BlkQSim uses a block‐oriented simulation order to reduce the block processing costs, while HyQSim can further reduce these costs by employing different simulation algorithms on qubits. This study conducts rigorous cost analysis and presents extensive experimental results, which show that compared with CompQSim, BlkQSim and HyQSim can achieve more than 4 and 107 speedups in block processing time, respectively.

In mobile systems, memory can be compressed page-by-page to save space. This approach is widely adopted because memory data is accessed by page. However, this paper shows that the system response speed is significantly limited by page-grained compression. In this paper, we observe that approximately a quarter of anonymous memory pages are highly correlated, even though the association is implicit. Inspired by this, we propose Archer, an association-rule-aware memory compression framework in mobile systems. Archer demonstrates that memory in mobile devices should be compressed using flexible granularity, rather than relying solely on traditional page compression. To further integrate association-rule mining techniques into system design, we redesign the LRU mechanism and propose an adaptive memory compression region. Experimental results show that the average app launching speed is 1.55x faster when enabling Archer, and the average photographic speed and frame rate increase by 1.42x and 1.31x, respectively, compared to the state-of-the-art.

With the development of autonomous driving, the data security of the collaboration between vehicles plays a more important role. The research of auto drive systems is still in its infancy, this paper shows that the security mechanisms either depend on hardware or introduce high latency. This paper proposes a novel data protection strategy for efficient coordination across vehicle systems. Our design is based on an observation that the security demand in different phases varies. Specifically, for the external system, this paper proposes an information security scheme with a fine-grained attribute selection mechanism, which has the flexibility of encryption attribute selection. For the internal system, this paper proposes a dual-channel RSA encryption scheme that makes the control information transmission more robust and saves encryption delay. Experimental results illustrate that both security and low latency can be ensured with the proposed SACC.

Racetrack Memory (RTM), as a promising next-generation memory technology, offers high storage density and low access latency. It is a potential alternative to DRAM in main-memory applications. However, the data access pattern of RTM differs from traditional memory. Its “shift before access” characteristic presents challenges for efficient memory management and rapid data access. This article proposes a novel address remapping algorithm for RTM to improve data access efficiency in these contexts. By analyzing memory access locality and computing weights based on trace patterns, our method distributes data across multiple banks to reduce access contention caused by sequential access within a single bank. In addition, we introduce a workload balancing mechanism to achieve wear leveling, which further optimizes overall parallelism and reduces performance bottlenecks in the RTM storage system. We evaluate the proposed algorithm on 15 real-world SPEC2006 benchmarks, which demonstrates that address remapping reduces the number of shifts by 10.9 % and the total bank energy by 10.1 %. Furthermore, our strategy leads to a 10.2 % reduction in the average latency of single trace. These results highlight the potential of RTM in main-memory applications where low energy consumption and high throughput are crucial. Additionally, they illustrate the effectiveness of our approach in optimizing RTM performance for real-world, latency-sensitive workloads.

Mobile devices have become ubiquitous in daily life. In contrast to traditional servers, mobile devices suffer from limited memory resources, leading to a significant degradation in the user experience. This paper demonstrates that the primary cause of memory consumption lies in anonymous pages associated with application heaps. Existing schemes are ineffective in deduplicating these pages due to the limited occurrence of the same anonymous pages. This paper presents Sparrow, a similar-page aware deduplication solution for mobile systems. Sparrow shows that memory pages still have the potential to deduplicate, even though the same pages are rare. An interesting observation inspires this, that is, a high number of pages having the partially-same contents. We have implemented Sparrow on real-life smartphones. Experimental results indicate that 30.45% more space can be saved with Sparrow.

Automatic test paper design is critical in education to reduce workloads for educators and facilitate an efficient teaching process. However, current designs fail to satisfy the realistic teaching requirements of educators, including the consideration of both test quality and efficiency. This is the main reason why teachers still manually construct tests in most teaching environments. In this paper, the quality of tests is quantitatively defined while considering multiple objectives, including a flexible coverage of knowledge points, cognitive levels, and question difficulty. Then, a model based on the technique of linear programming is delicately designed to explore the optimal results for this newly defined problem. However, this technique is not efficient enough, which cannot obtain results in polynomial time. With the consideration of both test quality and generation efficiency, this paper proposes a genetic algorithm (GA) based method, named dynamic programming guided genetic algorithm with adaptive selection (DPGA-AS). In this method, a dynamic programming method is proposed in the population initialization part to improve the efficiency of the genetic algorithm. An adaptive selection method for the GA is designed to avoid prematurely falling into the local optimal for better test quality. The question bank used in our experiments is assembled based on college-level calculus questions from well-known textbooks. The experimental results show that the proposed techniques can construct test papers with both high effectiveness and efficiency. The computation time of the test assembly problem is reduced from 3 hours to 2 seconds for a 5000-size question bank as compared to a linear programming model with similar test quality. The test quality of the proposed method is better than the other baselines.

Hotspot issue is ubiquitous in the in-memory key-value stores, which seriously affects its performance. The efficiency of the index structure is the key to the performance of the in-memory key-value store, and the access of hotspot data must be through the search of the index structure. However, the existing index structures do not consider the hotspot issue, they treat and manage all the data equally, and cannot break through the performance bottleneck of the system. Index structures of type B+-Tree are common in in-memory key-value stores, but the existing B+-tree index structures do not consider the frequent structure change caused by node restructuring, which will seriously degrade the performance of the index structure. In this paper, we propose LH-Index, an efficient flattened index structure with lazy restructuring and hotness awareness. First, we use a search method combining linear search and binary search based on a partitioning strategy and endow nodes in LH-Index with a hotness awareness ability to search hotspot data quickly. Meanwhile, we use a lazy restructuring strategy for LH-Index to reduce the performance degradation due to frequent structure change. In addition, in order to meet the requirements of most scenarios, LH-Index is extended to DRAM/NVM hybrid memory by separate storage. Our evaluation shows that LH-Index achieves up to 1.85x search throughput and the lowest tail latency relative to other index structures under highly-skewed workloads, and it also has the highest throughput under mixed workloads.

Scratch-pad memory (SPM) has been widely used in embedded systems because it allows software-controlled data placement. By designing data placement strategies, optimal solutions with minimal memory access latency for loops on SPM-DRAM architecture can be explored. Although existing works effectively reduce the latency by using fine-grained data placement methods, they fail in solving the case of inconsecutive array access. Meanwhile, fine-grained strategy can lead to excessive memory activation overhead, making it less efficient. Therefore, in this paper, we first propose a finegrained dynamic programming algorithm, called FiDP, to tackle unsolved case and minimize latency. In order to mitigate the frequent activation before data access, we then add a medium-grained scheme to our strategy. It can achieve a better solution than FiDP by strictly formulating an integer linear programming (ILP) problem and considering multiple granularities, which is called MuILP. Furthermore, to compensate for the high time complexity of ILP, we develop a heuristic multi-granularity data placement algorithm, called HMuDP, which achieves a near-optimal solution with lower complexity. Experimental results show that our FiDP reduces the total latency by 75.90%, 47.70% and 12.34% compared with LRU-cache, a greedy-based comparison method (called Uday) and a dynamic programming-based comparison method (called DLAA). Besides, our MuILP and HMuDP yield less latency than FiDP with 45.10% and 43.14% average improvement, respectively.

Intermittent embedded devices and systems are widely used in various scenarios, but they often experience power failures due to unstable power supplies. Non-volatile memory (NVM) is gaining popularity in embedded systems due to its byte-addressability, low access latency, and high density. As a result, backups can be stored in NVM, and global data are directly manipulated in NVM in this architecture. However, NVM has limited write endurance and modifications to global data frequently occur which results in a significant number of writes. As a result, the extensive NVM accesses may lead to poor performance for intermittent programs. This paper presents an energy -efficient approach, called shadow -stack to minimize NVM write overhead while ensuring consistency. Furthermore, we propose a series of principles to assist programmers in rewriting the programs. And we prove the correctness of these principles using formal methods. Experimental results demonstrate that shadow -stack achieves an approximately 95.1%, 81.3%, and 76.6% improvement in NVM writes overhead compared with log -based, Coach, and Clank, respectively on average. Simultaneously, shadowstack also significantly reduces energy and time consumption compared with log -based approach by up to 19.4x and 6.87x, Coach by up to 4.2x and 2.46x, and Clank by up to 3.4x and 2.26x respectively.

Embedded systems experience execution interruption due to power failures. After a power failure restarts, recovering the interrupted program from the initial state may lead to non-termination execution. To rapid recovery of program execution under power failures, the execution states are backed up by non-volatile memory (NVM) under power failures for embedded systems. However, frequent checkpoints will shorten the lifetime of the NVM and result in significant NVM write overhead, leading to low energy utilization in a power cycle. In this paper, we propose an incremental checkpoint approach called Call-Stack-Based to mitigate the NVM write overhead. It does not introduce additional run-time overhead when compared to other state-of-the-art methods. We introduce the pseudo-function call-stack-based strategy to further mitigate non-termination issues during execution. Simultaneously, we also propose an adaptive call-stack-based optimization strategy, a technique aimed at optimizing checkpoints within loops to enhance overall performance. To further prevent the NVM contents from becoming cluttered and taking up unnecessary space, we introduce a method to clean up irrelevant data on the NVM that is not required for restoration. In conclusion, the evaluation results demonstrate an average reduction of 99.88% and 88.71% in NVM write overhead for Call-Stack-Based backup compared to the Always-Based and Step-Based, respectively.

Personalized learning path recommendation is widely studied to address the cognitive overload and learning disorientation problem in e-learning platforms. Yet, how to recommend learning materials for learners so that targeting their learning objectives with the highest efficiency has not been addressed. Driven by this problem, this paper proposes a prototype to generate the most efficient learning strategies in the learning process for reaching learning objectives, it takes the learning ability of learners into consideration, and adaptively generates the optimal strategy in the learning process. A case that knowledge concepts have hierarchical relationships based on difficulty in one knowledge topic is studied, which is named series learning in this paper. Specifically, a learning state transition model is designed for selecting the optimal learning strategies in the learning process with the consideration of the changing learning ability of learners. Based on this model, a dynamically programming (DP) based method and a greedy-based method are designed to generate learning strategies with high efficiency. Experiments are conducted in both simulated and real learning scenarios. Results show that the proposed scheme significantly outperforms the baseline method.

Mobile systems and applications are becoming increasingly feature-rich and powerful, which constantly suffer from memory pressure, especially for devices equipped with limited DRAM. Swapping inactive DRAM pages to the storage device is a promising solution to extend the physical memory. However, existing mobile devices usually adopt flash memory as the storage device, where swapping DRAM pages to flash memory may introduce significant performance overhead. In this paper, we first conduct an in-depth analysis of the I/O characteristics of the flash-based memory swapping, including the I/O interference and swap I/O randomness in swap subsystem. Then an I/O efficiency optimization framework for memory swapping (IOSR) is proposed to enhance the performance of flash-based memory swapping for mobile devices. IOSR consists of two methods: swap I/O scheduling (SIOS) and swap I/O pattern reshaping (SIOR). SIOS is designed to schedule the swap I/O to reduce interference with other processes I/Os. SIOR is designed to reshape the swap I/O pattern with process-oriented swap slot allocation and adaptive granularity swap read-ahead. IOSR is implemented on Google Pixel 4. Experimental results show that IOSR reduces the application switching time by 31.7% and improves the swap-in bandwidth by 35.5% on average compared to the state-of-the-art.

Benefiting from numerous attractive characteristics, persistent memory (PM) has become a promising substitute for DRAM. Unfortunately, PM suffers from limited endurance of memory cells, especially with the unbalanced wears induced by applications. Even though several wear-leveling aware allocators have been proposed to prolong the lifespan of PM, they fail to perceive the endurance variation among memory cells, which may severely damage the weak cells. In this paper, we propose V-WAFA, a fine-grained PM allocator that considers endurance variation to improve the lifespan of PM. First, V-WAFA adopts a priority-based wear-leveling strategy to mitigate the side-effect of endurance variation among pages. Second, V-WAFA utilizes fine-grained space management and allocation strategy inside pages. Briefly, V-WAFA divides pages into basic units and allocates the basic units of a page in a rotational manner to evenly distribute fine-grained updates on memory cells. We implement V-WAFA in Linux 4.4.4 and evaluate it by running standard workloads on Redis, a typical in-memory key-value store. Evaluation results show that the wear-leveling effect of V-WAFA exceeds that of malloc, nvm_malloc, WAlloc, NVMalloc, and WAFA for 7.02×, 6.91×, 5.7×, 5.68×, and 3.78×, respectively. V-WAFA also achieves similar performance with state-of-the-art PM allocators on Redis running YCSB workloads.

Quantum circuit simulation is an important tool for evaluating designed quantum algorithms. Full-state simulation gives the entire state vectors produced by the running of algorithms. Distributed simulation aims to take advantage of resources on multiple machines (a.k.a. nodes) for high-performance simulation. As a quantum circuit may have many levels, simulation on each level is called a step. The reduction in the cost on each step results in a significant saving in total cost. In existing distributed full-state simulations, the communication cost in each step dominates. In this paper, we propose a new simulation technique, namely QuanPath, which completely eliminates communications and synchronizations on each step until the final merge step. Each node can compute its portion of the state vector independently in parallel. We present detailed mathematical analyses to guarantee the correctness of QuanPath. In the final merge step, an efficient communication scheme is further designed. Experimental results show that when simulating quantum algorithms, QuanPath achieves thousands times of reduction in communication cost and obtains dozens times of simulation acceleration compared with existing techniques. In addition, QuanPath realizes almost linear speedup, so it presents good scalability.

Non-volatile memory (NVM) is expected to be the second tier of memory in two-tier memory systems. However, because of the limited write endurance, it is vital to reduce the number of writes on NVM. Large-scale nested loops are the performance bottleneck in programs since the data cannot be held on the first tier of memory and then causes many write operations on NVM. Loop tiling groups iterations and loop interchange changes the execution order of the loop to improve data locality and thus reduce communication with NVM. However, research that combines loop interchange and loop tiling for minimizing writes on NVM is uncommon. In this paper, we propose a new loop tiling scheme and combine the loop interchange to solve these issues. Specifically, we propose a strategy to generate the legal tile shape, which is a parallelogram, first. Then, we propose an optimal tile size selection technique to minimize the write operations on NVM. In addition, we adopt the loop interchange technique to help loop tiling generate an optimal tile size for multi-dimensional loops. Finally, we schedule the accessing operations and computations in a pipeline fashion to cover the NVM latency. Experiments show that the proposed scheme can reduce the write on NVM efficiently. In addition, for 2-dimensional loops, NVM latency can be completely hidden.

Predicting hard disk failure effectively and efficiently can prevent the high costs of data loss for data storage systems. Disk failure prediction based on machine learning and artificial intelligence has gained notable attention, because of its good capabilities. Improving the accuracy and performance of disk failure prediction, however, is still a challenging problem. When disk failure is about to occur, the time is limited for the prediction process, including building models and predicting. Faster training would promote the efficiency of model updates, and late predictions not only have no value but also waste resources. To improve both the prediction quality and modeling timeliness, a two-layer classification-based feature selection scheme is proposed in this paper. An attribute filter calculating the importance of attributes was designed, to remove attributes insensitive to failure identification, where importance is gained based on the idea of classification tree models. Furthermore, by determining the correlation between features based on the correlation coefficient, an attribute classification method is proposed. In experiments, the models of machine learning and artificial intelligence were applied, and they included naïve Bayesian, random forest, support vector machine, gradient boosted decision tree, convolutional neural networks, and long short-term memory. The results showed that the proposed technique could improve the prediction accuracy of ML/AI-based hard disk failure prediction models. Specifically, utilizing random forest and long short-term memory with the proposed technique showed the best accuracy. Meanwhile, the proposed scheme could reduce training and prediction latency by 75% and 83%, respectively, in the best case compared with the baseline methods.

In this paper, a novel hybrid scratchpad memory (SPM) with SRAM and racetrack memory (RM) is proposed. The basic idea is to smartly place data on SPM by taking the advantages of these two memories. First, a metric is proposed to represent the access cost of data; Second, a data placement scheme is proposed based on the metric; Finally, to maximize the size of SPM, a scheme is further proposed to minimize the size of SRAM. Experimental results show that the proposed scheme reduces the shift operations of RM by 80.12% and reduces the cost of SPM by 80.72% with only 17.63% SRAM compared with a baseline SPM with pure RM.

Along with the progress of artificial intelligence (AI) democratization, there is an increasing potential for the deployment of deep neural networks (DNNs) to tiny devices, such as implantable cardioverter defibrillators (ICD). However, tiny devices with extremely limited energy supply (e.g., battery) have high demands on low-power execution, while guaranteeing the model accuracy. Stochastic computing (SC) as a new promising paradigm significantly reduces the power consumption of DNNs by simplifying arithmetic circuits, but often sacrifices the model accuracy. To make up for the accuracy loss, previous works mainly focus on either only-hardware (only-HW) circuit design or software-to-hardware (SW -> HW) sequential workflow, which leads to unilateral optimization. Therefore, as the first attempt, aiming at both the hardware (HW) and software (SW) performance, we innovatively propose an HW <-> SW co-exploration framework for SC-based NNs, namely SC-NAS, which is the first to couple SC with neural architecture search (NAS) for HW/SW co-optimization. We redefine the optimization problem and show a complete workflow to intelligently search for a set of configurations of NNs with hardware consumption as low as possible and accuracy as high as possible. We comprehensively explore the influencing factors, which have impacts on both the HW and SW performance for SC-based NNs, to build a search space for NAS. Furthermore, in order to improve the search efficiency of NAS, we contract the search space and set an energy constraint to early terminate unnecessary model inference. Experiments show that SC-NAS achieves up to 7.0 x energy saving than FP-NAS, and exceeds pure SC methods by over 3.8% in accuracy. Meanwhile, SC-NAS obtains around 8.6 x 1019 x search efficiency improvement than exhaustive search using VGGNet.

Racetrack memory (RTM), which consists of multiple domain block clusters (DBC) and access ports, is a novel non-volatile memory and has potential as scratchpad memory (SPM) in embedded devices due to its high density and low access latency. However, too many shift operations decrease the performance of RTM and cause un-predictable performance. In this paper, we propose three schemes to optimize the performance of RTM from different aspects, including intra-DBC, inter-DBC, and hybrid SPM with SRAM and RTM. Firstly, a balanced group-based data placement method for the data layout inside one DBC is proposed to reduce shifts. Second, a grouping method for the data allocation among DBCs is proposed. It helps with the shift reduction while using fewer DBCs by using one DBC as multiple DBCs. Finally, we use SRAM to further help the cost reduction, and a cost evaluation metric is proposed to assist the shrinking method which determines the data allocation for hybrid SPM with SRAM and RTM. Experiments show that the proposed schemes can significantly improve the performance of pure RTM and hybrid SPM while using fewer DBCs.