An innovative lateral superjunction (SJ) power metal-oxide-semiconductor field-effect transistor (MOSFET) structure with a surface-deposited high-k (HK) film is proposed. Through field-responsive modulation of bound charges at the HK film interface, the proposed structure adaptively screens electric field perturbations in the N-Drift, thereby mitigating the charge-imbalance issue in conventional lateral SJ devices. Simulation results indicate that the specific on-resistance of the proposed structure is reduced by 24% compared with the conventional SJ structure under the same breakdown voltage. Furthermore, the proposed structure exhibits a P-region charge-imbalance process window ranging from −8.0% to 16.0%, which is 27.7% wider than that of the conventional SJ structure. It also achieves an interface charge process window of −1.5×1011 cm−2 to 3.6×1011 cm−2, which is 410% wider than that of the SJ structure. These results demonstrate that the proposed structure simultaneously improves device performance and charge imbalance immunity, providing a novel solution for enhancing the reliability and engineering application potential of lateral SJ MOSFETs.

This paper investigated a novel silicon carbide (SiC) trench MOSFET with integrated N+-PolySi/SiC HeteroJunction diode (nHJ-TMOS) on the trench sidewalls to realize low power loss and high temperature stability. Compared to the conventional double-trench MOSFET (DT-MOS), simulation results indicate that the nHJ-TMOS significantly reduces the reverse on-state voltage drop (V-R_on) from 3.7 to 1.6 V, due to the integration of the N+-PolySi/SiC heterojunction diode (nHJD), which features a low barrier height of similar to 0.70 eV. By reducing the depth of the gate trench, nHJ-TMOS effectively mitigates the electric field crowding effect at the corners of the gate oxide, obtaining a low electric field of only 2.1 MV/cm. Besides, this shallow gate trench reduces the gate-to-drain capacitance (C-GD) by 30.9%. Moreover, due to unipolar conductivity of the nHJD, the reverse recovery charges (Qrr) of nHJD is reduced by 26.7% and 59.5% under 25 degrees C and 175 degrees C, respectively. Consequently, the turning-on power loss of the nearby switch is reduced by 27.3% and 38.1%, respectively. This provides distinguished advantages for the SiC MOSFET in high power applications.

In this letter, a novel 4H-SiC/Diamond Super Junction (SJ) MOSFET with a Self-driving Electron Accumulation Layer (SD-EAL) in the drift region, named as SD-EAL MOSFET, is proposed and investigated based on experimentally calibrated TCAD simulations. The SJ structure comprising n(4H-SiC)/Al2O3/p(Diamond) is used for feasible fabrication and formation of EAL. An integrated self-biased low-voltage power formed by integrated JFET structure, PolySi PN diode and MIS capacitor is designed to automatically drive the p-pillar, thus forming an EAL during on-state and significantly reducing the specific on resistance (R (on,sp)). The simulated breakdown voltage (BV) of the SD-EAL reaches similar to 1.6 kV, with R-on,R-sp being only 0.75 m Omegacm(2), which is 36% lower than that of conventional SJ (C-SJ). Compared to the C-SJ MOS-FET, Figure of Merit for the SD-EAL MOSFET reaches 5.69 GW/cm(2), which is improved by 94%. Thus, the SD-EAL can be an excellent candidate for future high-voltage SJ MOSFET.

In this article we propose a 600 V rated 4H-SiC trench MOSFET integrated with an n-PolySi/4H-SiC heterojunction tunneling transistor (named as nHJTT-MOS) and calibrated simulations are used to demonstrate the advantages of the proposal. The trench gate is semi-enclosed by n-PolySi and a heterojunction of n-PolySi/4H-SiC is formed. A P+ shielding layer surrounding the n-PolySi is used to protect the pre-breakdown of PolySi and gate oxide. When VGS is high, high electron densities accumulated on two sides of the n-PolySi/4H-SiC, which forms a low resistive channel for the electron tunneling current. Thus, much lower specific on-resistance (Ron,sp) can be obtained especially for 600 V rated SiC MOSFETs. In the reverse conduction state, the n-PolySi/4H-SiC heterojunction diode inactivates the PN body diode and the reverse on-state voltage (VR_on) is significantly reduced. Calibrated simulations demonstrate that Ron,sp and VR_on of nHJTT-MOS are only 0.73 m Omega & centerdot;cm2 and 0.84 V, which are reduced by 26.3% and 0.87 V compared with those of the p-PolySi-based trench MOSFET. The proposed nHJTT-MOS shows high potential for SiC trench MOSFET at the middle-low voltage level, in which the low channel mobility significantly hinders the reduction of Ron,sp.

Abstract A novel trench 4 H-SiC MOSFET integrating an n + -PolySi/p-PolySi/n-SiC sidewall heterojunction tunneling channel , named HTC-MOS, is proposed and investigated by calibrated TCAD simulation. In the proposed HTC-MOS, one channel is realized by n + -PolySi/p-PolySi/n-SiC. Under positive gate bias, the p-PolySi interface is inverted into an electron inversion layer and the n-SiC interface accumulates a large amount of electrons, which forms an n + -PolySi/n + -SiC interface enabling significant tunneling current across the heterojunction. This tunneling-induced current path and the traditional SiC inversion channel form a dual-channel conduction path that lowers the overall channel resistance. In the reverse free-wheeling state, the p-PolySi/n-SiC heterojunction ensures lower reverse on-state voltage drop ( V R_on ) and reverse recovery charge ( Q rr ) owing to unipolar conduction. Simulation results show that the 1.2 kV rated HTC-MOS achieves an R on,sp of 1.46 mΩ·cm 2 , reduced by 24.0% compared with that of a conventional device ( R on,sp = 1.92 mΩ·cm 2 ). The V R_on is reduced from 2.96 V – 1.82 V, representing a 38.5% reduction. Q rr is reduced by 25.7%, which contributes to a 7.5% reduction in turn-on power loss.

In the design of power metal-oxide-semiconductor field-effect transistor (MOSFET) devices, balancing high breakdown voltage (BV) with low specific on-resistance (R-on,R-sp) remains a long-standing challenge. In this work, we proposed and simulated a novel Double-RESURF beta-Ga2O3 metal-insulator-semiconductor field-effect transistor (MISFET) with varied-lateral doping (Double-RESURF-VLD MOSFET). By embedding alternating n-type and p-type pillar of diamond regions into the VLD channel, the Double-RESURF structure enables effective charge compensation, which allows higher drift-layer doping concentration without sacrificing BV, thereby significantly reducing R-on,R-sp. Simulation results show that the Double-RESURF-VLD MOSFET achieves a R-on,R-sp of 2.58 m Omegacm(2), a reduction of more than 50% compared with 6.73 m Omegacm(2) of the conventional VLD MOSFET. Meanwhile, the BV of the Double-RESURF-VLD MOSFET reaches 2.99 kV, representing a 30% improvement over the VLD-MISFET. In addition, the Baliga's figure of merit (BFOM = BV2/R-on,R-sp) is improved to 3.47 GWcm(-)(2), representing an increase of approximately 310% compared with 0.84 GWcm(-)(2) of the conventional VLD-MISFET. These results demonstrate that the proposed Double-RESURF-VLD MOSFET offers a promising candidate for the next-generation of beta-Ga2O3 power devices with superior trade-offs between BV and R-on,R-sp.

In this letter, a novel 3C-SiC/Ga2O3 Hetero-Channel Ga2O3 MISFET (3C-HC-MISFET) for enhancement-mode (E-mode) operation, low specific on-resistance (R-on,R-sp) and low reverse on-state voltage drop (V-R_ON) is proposed and demonstrated by experimentally calibrated TCAD. A p-type 3C-SiC layer is directly bonded atop beta-Ga2O3 to form the inversion channel for E-mode operation. A heavily doped p-NiO layer under the trench gate suppresses the electric field in the gate dielectric. Besides, the p-NiO/Ga2O3 interface forms a low-barrier Heterojunction diode (HJD), which significantly reduces V-R_ON. The simulated BV of the 3C-HC-MISFET reaches similar to 2.7 kV with R-on,R-sp being only 1.44 m Omega cm(2), 12 % lower than that of the GaN limit. Compared to the conventional Fin-gate MISFET (FG-MISFET), Baliga's Figure of Merit of the 3C-HC-MOSFET reaches 5.17 GW/cm(2), which is improved by 320 %. Moreover, the maximum temperature rise (T-rmax) of the proposal under the continuous current-pulse test reduces by 29 K compared to FG-MISFET. Therefore, the 3C-HC-MOSFET is a promising candidate for high-voltage E-mode Ga2O3 power devices.

A GaN-on-Si vertical gallium nitride high-electron-mobility transistor that fully utilizes two-dimensional electron gas (2DEG) to conduct is proposed. The proposed structure is based on the anisotropic etching technique to form V-shaped grooves with (111)-oriented sidewalls on the Si substrate, on which an AlGaN/GaN heterostructure is grown to enable a vertical distribution of 2DEG, thereby significantly reducing the specific on-resistance and the energy loss per switching cycle. Compared to the GaN trench-gate MOSFET, and under the condition of identical threshold voltage ( Vth) and breakdown voltage, the proposed structure exhibits a specific on-resistance ( Ron,sp) of 0.16 m Omega & sdot;cm2 and a single-cycle energy loss of 36.8 mu J at a switching frequency of 200 kHz, corresponding to reductions of 60.98% and 41.25%, respectively. The results indicate that the proposed structure has great potential for future high-power switching applications.

In this paper, we propose and investigate a novel 4H-SiC MOSFET with integrated N+-PolySi/N-SiC heterojunction diode (named as nHJD-MOS) by calibrated TCAD simulation. An N+polysilicon region is set on the top of the drift region and connected to the source electrode to form a $\mathrm{N}^{+}-\text{PolySi} / \mathrm{N}-\text{SiC}$ heterojunction diode (nHJD), which is used to inactivate the body diode. Thus, the third quadrant performance and switching performances are improved. The numerical simulation results show that the specific on-resistance $({R}_{\text{on}, \text{sp}})$ and breakdown voltage (BV) of the nHJD-MOS are ${1. 9 7} \mathrm{m} \Omega \cdot \text{cm}^{2}$ and 1565 V, respectively. At a current density of 300 $\mathrm{A} / \text{cm}^{2}$, the reverse on-state voltage drop $(V_{\mathrm{R}\_\text{on }})$ is 1.42 V, which is 2.08 V lower than that of the Conventional MOS (Con-MOS). Furthermore, reverse recovery charge $(Q_{\text{rr}})$ and turning-on power loss $(E_{o n})$ are also reduced by 17.8 % and 6.3 %, respectively. In addition, under high temperatures, $E_{\text{on }}$ of the Con-MOS increases significantly due to increased $Q_{\text{rr }}$. While, $E_{\text{on }}$ of the nHJD-MOS almost remains unchanged due to unipolar conduction of the HJD.

A beta-Ga2O3 trench Schottky barrier diode (T-SBD) with double-field-plates terminal and cost-effective Al2O3/SiN dielectric layer is fabricated. Owing to the shielding effect of the trench metal-Insulator-semiconductor structure, compared with conventional SBD (C-SBD), the breakdown voltage of the T-SBD is improved from 700 V (C-SBD) to 1380 V (T-SBD) with specific on-resistance (Ron,sp) being 6.06 m Omegacm2. Compared to C-SBD, Baliga's figure of merit for the T-SBD is improved from 131 MW cm-2 (C-SBD) to 314 MW cm-2 (T-SBD). Moreover, the leakage current of T-SBD is significantly reduced from similar to 0.33 mA cm-2 (C-SBD) to similar to 38 mu A cm-2 (T-SBD).

A high-voltage fin-gate beta-Ga2O3 Metal Insulation Semiconductor Field Effect Transistor with dynamic channel barrier (DCB-MISFET) is proposed and verified by experimentally calibrated TCAD simulations. The DCB is achieved by a p-NiO trench adjacent to the gate. In forward conduction, the effective channel barrier height is increased and a high threshold voltage is obtained owing to the p-NiO/Ga2O3 interface. In reverse conduction, the intrinsic low channel barrier enables a low reverse on-state voltage drop VR_on (similar to 2.1 V, 47.5% lower than the conventional fin-gate MISFET (FG-MISFET)). In addition, the p-NiO shields the bottom of the gate dielectric, improving the breakdown voltage (BV) and reliability. The DCB-MISFET with single gate (Case I) and double gate (Case II) has a BV of 2322 V and 1835 V with a specific on-resistance (Ron,sp) of 2.05 m Omegacm2 and 1.80 m Omegacm2. Compared to the FG-MISFET (BV = 1310 V, Ron,sp = 1.55 m Omegacm2), Baliga's figure of merit improves by 137% and 68% for Case I and Case II, respectively. The gate charges (QG) for Case I and Case II reduce by 59% and 42%. Moreover, the total switching loss is reduced by 64% for Case I and 57% for Case II due to the lower CGS and CGD.

In this paper, a novel nanomembrane beta-Ga2O3 MISFET (NM-MISFET) with double linearly-doped drift layer to realize near-rectangle electric field is proposed, which obtains the highest Baliga's Figure of Merit (BFOM) of lateral Ga2O3 MISFETs. By setting two grounded field plates on the top and bottom of the whole linearly-doped drift layer, the thickness of the drift layer can be doubled, which significantly reduces the specific on-resistance (R-on,R-sp), and the highest BV can be realized since uniform electric field is realized. A simple analytical model for breakdown voltage (BV) is proposed and verified by TCAD simulation. Furthermore, NM-MISFETs with BV similar to 3 kV is designed to demonstrate the advantages of the device. Ultra-low R-on,R-sp of 1.78 m Omega cm(2) is realized, leading to high BFOM. Considering fabricated processes, NM-MISFETs using segmental doping in drift region are discussed. Drift region is uniformly divided into 2, 3, and 4 segments to simulate and corresponding NM-MISFETs reach 89 %, 95 %, and 96 % of BV of linearly doped NM-MISFET.

In this paper, a novel SiC MOSFET with an integrated Junction Barrier Schottky diode (JBS) on the surface (named JBS-MOS) is proposed, which enhances the reverse conduction capability and reduces the switching losses, offering superior performances in power converter applications. Simulation results show that the specific on-resistance $({R}_{\text{on}, \text{sp}})$ and breakdown voltage (BV) of the JBS-MOS are ${1. 9 0 m \Omega \cdot c m ^{2}}$ and 1604 V, respectively. Meanwhile, JBS-MOS achieves a reverse onstate voltage $(V_{\mathrm{R}\_ \text{on }} {@} J_{\text{DS }}=-300 \mathrm{A} / \text{cm}^{2})$ of 1.91 V, reduced by 1.59 V compared to Conventional MOSFET (C-MOS). Additionally, its reverse recovery charge $(Q_{\text{rr}})$ is reduced by 78.7% at 450 K, resulting in a 53.7% reduction in turn-on loss at 450 K, indicating improved switching efficiency. These simulation results indicate that the JBS-MOS has potential for high-power and hightemperature applications.

An analytical Superjunction (SJ) structure with two zones variation vertical doping profile (VVD-SJ) is proposed in this article. The 2-D electric field distributions are derived by charge superposition method. Optimization is carried out based on the MATLAB. The validity of the electric field distributions, breakdown voltage (BV) and impact ionization integral are demonstrated by TCAD MEDICI. The optimized results show the R on,sp of the VVD-SJ can be reduced by ~16% compared with that of convention SJ.

A new field plate (FP) is proposed for gallium nitride high-electron-mobility transistors (HEMTs). It features an innovative arcuate end (AE), which allows the induced charges that originally gathered at the FP end to diffuse over a wider area. Hence, not only is the electric field in the channel at the gate edge alleviated due to the induced charges, but also that concentrated at the FP end is reduced by means of AE. The simulation results indicate that by upgrading a source FP with AE, HEMT gains a 99% increase in breakdown voltage while remaining unaltered in specific on-resistance. It also gets a 43.41% decrease in power loss during one cycle while maintaining the same breakdown voltage, which greatly contributes to enhance the efficiency of power electronic circuits. This work reports a new field plate technique for the popular device of gallium nitride high-electron-mobility transistors. The proposed technique solves the inherent shortcomings of the traditional field plate technology, and significantly improves the device performance and reliability. image

A novel structure of p-GaN high-electron-mobility transistor (HEMT) is proposed and studied. It features two composite layers. One is the composite passivation (CP) layer consisting of Si3N4 and high-permittivity (HK) film. The other is a composite barrier (CB) layer consisting of AlxGa1-xN/AlN/Al0.23Ga0.77N. Due to the coordinated effect of CP and CB, the specific on-resistance (R-ON,R- SP) can be reduced under the premise of ensuring breakdown voltage (BV). Meanwhile, since the HK film in CP introduces a mechanism to automatically compensate the hot electrons trapped by surface states, the current collapse effect could be suppressed. According to the simulation results, in comparison with the conventional p-GaN HEMT, the proposed one using TiO2 as the HK material and using Al-component of 0.35 for AlxGa1-xN gains a 29.5% reduction in R-ON,R- SP while getting a 9.8% increase in BV, which contributes to a 50.5% decrease in the energy loss during one cycle at 200 kHz. It is also demonstrated by the simulation results that the current collapse in the proposed device is reduced by 28.6%. Thereby, a promising p-GaN HEMT with improved performance and reliability is invented.

In this letter, a novel 4H-SiC/Ga2O3 Hetero-Channel Ga2O3 MISFET (HC-MISFET) for E-mode operation and low reverse conduction loss is proposed and demonstrated by experimentally calibrated TCAD. A p-type 4H-SiC is integrated on the top of Ga2O3 to form the inversion channel for E-mode operation. A deep trench p-NiO near the trench gate is firstly used to suppress the electric field in the Al2O3 gate dielectric and improve the dielectric breakdown voltage (BV). Besides, reverse p-NiO/n-Ga2O3 Heterojunction diode (HJD) and 4H-SiC/p-NiO Hetero-Channel Diode (HCD), having a low turn-on voltage, are integrated to reduce the reverse free-wheeling loss. The simulated BV of the HC-MISFET reaches similar to 3.58 kV (considering a reliable Al2O3 electric field of 5.3 MV/cm) with specific on-resistance (R-on,R-sp) being 7 m Omega.cm(2). Compared to Fin-gate MISFET, Baliga's Figure of Merit of the HC-MISFET reaches 1.83 GW/cm(2), which is improved by 60.5%. Besides, the turning-on and turning-off power loss are reduced by 26% and 65%, respectively. Moreover, the maximum temperature raise in every switching period is reduced by 1.5 K and 9.9 K for the free-wheeling device and switching device, respectively.

In this paper, a recessed-gate ${\beta}-{\text{Ga}_2\mathrm{O}_{3}}$ MOSFET is investigated by TCAD. Enhanced mode is obtained by etching the channel layer to be 40 nm. High breakdown voltage and low specific on-resistance $({R}_{\text{on.sp}})$ is obtained by optimizing the field plate length and SiO2 thickness for the gate and drain field plates, as well as the doping concentration of the channel layer. Simulation results show that when the gate and drain field plates are 4 μm and 2 μm with SiO2 thickness being 500 nm, the device obtains a BV of 4256 V and ${R}_{\text{on,sp=23.3m}\Omega\cdot \text{cm}^{2}}$, showing a high Baliga's Figure of merit of $777.4 \text{MW/cm}^{2}$.

To solve problems of parasitic effects in interconnects, low reliability, and three-dimensional stress associated with 3D heterogeneous and stacking of small chips, the complete process and model research of a 6-inch 20V GaN/Si CMOS 1P2M/(111) Si monolithic heterogeneous integration in the paper is put forward at the first time. Innovations have been made in high-quality patterned selective epitaxy of GaN, compatibility of GaN/Si-based P-well CMOS processes, and platformed device design. This work has overcome several engineering challenges associated with the process integration of 6-inch Si CMOS IC and GaN IC chips, leading to the development of key devices such as (1) Si PMOS with a threshold voltage/current drive (VTH/IDS (forward)) of -0.7V, 2.5 mA/mm; (2) high-performance bulk silicon PN diodes with a forward voltage (VF) of about 0.72~0.79 V; (3) PNP and NPN silicon bipolar devices with β of approximately 260 and 300, respectively; (4) AlGaN/GaN HEMTs with VTH/IDS (forward) of -3V, 300–500 mA/mm. A prototype platform for heterogeneous integration processes, including Si CMOS and GaN processes, has been established.