A fully differential offset-stabilized amplifier with a two-step dynamic offset calibration achieving sub-& micro;V offset and a 55 MHz gain-bandwidth product (GBW) is presented. The twostep offset calibration combines digitally-assisted auto-calibration with dynamic offset compensation (DOC) that maintains ultralow residual offset. The slow-settling auto-zeroing (AZ) technique is integrated with a proposed chopping scheme, which suppresses noise across the entire bandwidth, enabling higher bandwidth operation with reduced ripple and noise aliasing. Fabricated in a 180 nm BCD process, the prototype occupies an area of 1.32 mm(2). The measurements show that the input-referred offset standard deviation is reduced by 99.97%, from 0.8 mV to 206 nV. Furthermore, the noise spectrum is nearly flat with the high-frequency ripple effectively suppressed. A noise floor of 7.8 nV/root Hz has been achieved, corresponding to a noise efficiency factor (NEF) of 15. These results demonstrate its potential to be widely adopted in high-accuracy and high-bandwidth applications.

The wearable electrocardiogram (ECG) sensor has immense potential for cardiovascular healthcare monitoring. However, uploading ECG signals to server-side devices for diagnosis poses privacy risks. Multi-tasking ECG processors rely on multi-beat windows and complex models, leading to high latency and energy consumption that limit deployment in resource-constrained wearable devices. In this work, we present a single-lead ECG sensor for authenticated healthcare that performs QRS complex detection (Task 1), arrhythmia detection (Task 2), bio-identification (Task 3), and bio-authentication (Task4). This sensor uses an invariant spectrum feature extractor on dual-mode single-beat ECG segments to derive normalized biometric features for these tasks, reducing the record latency to a single beat. A binary neural network (BNN) model is used for multi-task decision-making, achieving an accuracy of >94% across all tasks in the MIT-BIH database while reducing the model size to 5.725 kB. The sensor, implemented in 55-nm technology, occupies 0.50 mm(2), with the digital processing core (DPC) occupying 0.27 mm(2). Operating at a 0.85-V supply and 320-kHz clock, the DPC achieves a task latency of 1.04 s, representing a 2 & times; - 12 & times; reduction compared to state-of-the-art work, with inference energy of 0.19 mu J/task ( 3.7 & times; - 26 & times; reduction).

Brain–computer interfaces (BCIs) have advanced at a rapid pace in recent years, particularly in the medical domain. This review provides a comprehensive summary of the progress made in medical BCIs during the 2023–2024 period, covering a wide range of topics from invasive to non‐invasive techniques, and from fundamental mechanisms to clinical applications. The 2023–2024 period saw numerous research breakthroughs and clinical applications of BCI technology. As BCI hardware and software continue to evolve, and as the understanding of basic medical principles deepens, the expectation is that innovative BCI inventions will increasingly be introduced in clinical practice. Both invasive and non‐invasive BCI technologies are paving the way for broader clinical applications. It is anticipated that BCI technologies will offer greater hope for disease treatment, provide additional methods of enhancing human bodily functions, and ultimately improve the quality of life.

This paper presents a bioinspired, multi-channel auditory signal encoder based on volatile memristors, designed to mimic the short-term adaptation behavior of the human auditory system. The system integrates a threshold generator with an asynchronous delta modulator (ADM) to dynamically adjust threshold voltages based on real-time memristor behavior. The encoder is implemented with standard 130nm CMOS technology, occupying a compact area of 0.44 mm x 0.185 mm per channel and consuming 299.85 mu W per channel. The adaptive resolution of the encoder is validated in simulations using a memristor model derived from real device data, demonstrating adaptive output firing rates as a result of memristor resistance volatility. With a maximum delay of 45.25 ns for a 1 kHz sound input, the design is well-suited for spike-domain neuromorphic systems.

Brain-computer interfaces (BCIs) represent an emerging technology that facilitates direct communication between the brain and external devices. In recent years, numerous review articles have explored various aspects of BCIs, including their fundamental principles, technical advancements, and applications in specific domains. However, these reviews often focus on signal processing, hardware development, or limited applications such as motor rehabilitation or communication. This paper aims to offer a comprehensive review of recent electroencephalogram (EEG)-based BCI applications in the medical field across 8 critical areas, encompassing rehabilitation, daily communication, epilepsy, cerebral resuscitation, sleep, neurodegenerative diseases, anesthesiology, and emotion recognition. Moreover, the current challenges and future trends of BCIs were also discussed, including personal privacy and ethical concerns, network security vulnerabilities, safety issues, and biocompatibility.

This brief presents a low-input-bias-current (I-B), high-precision CMOS operational amplifier utilizing an automatic offset calibration (AOC) technique. The proposed AOC incorporates a BOXCAR switched-capacitor (SC) integrator to improve calibration accuracy without degrading I-B and input impedance. The prototype has been implemented in a standard 0.18-mu m complementary metal-oxide-semiconductor (CMOS) process. Simulation results show that an intrinsic input offset voltage (V-os) ranging up to +/- 2.6 mV can be calibrated within 500 mu s, achieving a residual V-os of 12 mu V. Benefiting from the reduced Vos, the common-mode rejection ratio (CMRR) is improved to 108.7 dB. An extremely low typical I-B of 18 fA makes the prototype well suited for high-precision and high-impedance interfaces that require wide bandwidth.

This work presents a fully differential, offset-stabilized amplifier achieving sub-mu V offset and a 55 MHz gain-bandwidth product (GBW). A two-step offset calibration strategy is employed, combining digitally-assisted auto-calibration with dynamic offset compensation (DOC). Slow-settling auto-zeroing (AZ) is integrated with chopping through a customized clocking scheme, enabling bandwidth extension without compromising offset and noise performance. Implemented in a 180 nm BCD process, the prototype occupies an area of 1.32 mm(2). Simulation results show a 3s input-referred offset reduction from 1.6 mV to 615 nV and a nearly flat low-frequency noise spectrum without tones at the switching frequency. A noise floor of 7 nV/v Hz has been achieved, corresponding to a noise efficiency factor (NEF) of 13. These results demonstrate its potential to be widely adopted in high-accuracy and high-bandwidth applications.

Techniques for the foreground calibration of split capacitor successive approximation register (SAR) are discussed. The used methods of digital calibration requires a digital post-processing that can be a limit for the resulting overhead. The presented techniques allow directly obtaining the digital output. Two methods address the mismatch among the unit elements in the most significant byte (MSB) segment and the mismatch at the MSB-LSB interface. A 16-bit SAR ADC with a sampling rate of 1MS/s employs both calibration techniques and verifies the methods. The simulation results show a Schreier merit of 166.3 dB, a signal-to-noise-and-distortion ratio (SNDR) of 87 dB, and an SFDR of -100 dB. A chip fabricated in a 180-nm Bipolar-CMOS-DMOS (BCD) process almost obtains the expected SNDR. The experimental result shows that the spurious-free dynamic range (SFDR) improves from 70.71 to 93.29 dB.

This work presents a single-inductor multi-source energy harvester capable of simultaneously collecting energy from up to two DC sources and one AC source while regulating three loads with the support of a super capacitor. The proposed architecture incorporates a hybrid buck-boost/boost circuit as well as a double pile-up circuit for AC and DC energy harvesting respectively. It facilitates multi-source maximum power point tracking (MPPT) and multi-load regulation within a single cycle, efficiently storing and reusing surplus ambient energy with the assistance of the super capacitor. The harvester dynamically adapts to its operating environment, automatically switching between various working modes based on the available energy sources and the demand of the output loads. Implemented in 180 nm BCD process, the prototype occupies a total area of $2.5 \mathrm{~mm}^{2}$. Simulation results demonstrate successful transitions from self-start-up (SSU) mode to multi-source energy harvesting and multi-load regulation (MSEH-MLR) mode, achieving a 49.7 nA quiescent current with a peak efficiency of 83.8%. The PZT energy extraction improvement is 719%, increasing by 159% compared to the state-of-the-art works.

This article presents an on-chip self-calibrated pseudo-resistor (PR) based on a sigma-delta modulation (SDM) loop. The proposed real-time calibration mechanism facilitates the implementation of an accurate low-drift ultra-high-value (UHV) PR with a wide tuning range at minimum hardware expenditure. Experimental results demonstrate that the resistance can be precisely tuned from 1.5 G Omega to 2.5 T Omega . The average temperature drift is 0.12%/degrees C within the temperature range from - 40 degrees C to 80 degrees C, which is comparable to the on-chip high-resistance poly resistor. The relative accuracy ( 3 sigma/mu ) is 25.8% under room temperature, representing an improvement of over one order of magnitude compared to an uncalibrated PR. To validate the proposed calibration loop, a capacitively-coupled instrumentation amplifier (CCIA) embedding the calibrated PR has been fabricated in a standard 180-nm CMOS process, occupying a core area of 0.187 mm(2). The CCIA achieves an accurately tunable high-pass corner frequency ( f(HP) ) from 0.13 to 217 Hz, a total harmonic distortion (THD) as low as 0.0093%, and a linear output swing up to 3.9 V-PP. The input-referred noise (IRN) is measured at 2.40 mu V-rms within a 0.5-200-Hz bandwidth. In conclusion, this work paves the way for implementing accurate tunable on-chip UHV resistors in mass production.

This article presents a two-step direct-conversion front-end (Direct-FE) for noninvasive wearable biomedical devices. In the first step, a delta modulator (Delta M) with embedded gain is used to implement coarse quantization, while in the second step, a discrete-time sigma delta modulator (DT- Sigma Delta M) is used to realize fine quantization. DC-coupled differential difference amplifier (DDA) with resistor-based digital-to-analog converter (RDAC) is adopted as the input stage. Mismatch error shaping (MES) with reduced silicon area is utilized to suppress the mismatch error of the RDAC. The prototype has been implemented in 0.18- mu m BCD process and achieves a peak input range of 7.64 V-pp , an input-referred-noise (IRN) of 1.59 mu V-RMS , a corresponding dynamic range (DR) of 115.2 dB, while consuming 2.4-mW power. The real physiological signals recording demonstrates its potential capability for wearable bio-potential acquisition, boosting the wearable and fitness application areas.

The residual charge accumulated across the electrode tissue interface during electrical neurostimulation causes severe tissue damage and electrode corrosion. By minimizing this charge, the lifespan of a neurostimulation system can be prolonged, necessitating the development of precise charge-balancing technologies. This paper presents an 11.3 V -compliant currentcontrolled neurostimulation circuit employing a two-step charge balancing technique. Implemented in a 180 nm BCD process, the stimulator chip occupies a core area of $0.88 \mathrm{~mm}^{2}$. Simulations results demonstrate that the prototype can source or sink currents up to 2.5 mA with a 4-bit resolution, while maintaining the residual voltage below $537 \mu \mathrm{~V}$. The proposed two-step chargebalancing technique reduces the standard deviation of the steadystate residual voltage by 95.1% compared to conventional singlestep method, whereas the increased charge-balancing time is merely 1.3% at an initial residual voltage of 1 V.

Multi-channel multiplexing front-ends based on current domain-frequency division multiplexing (CD-FDM) can alleviate the contradiction between higher single-channel power and the number of channels. Direct digital conversion (DDC) architecture eliminates the amplification stage, saving power consumption and area. However, research on multi-channel DDC is still lacking up to date. This brief demonstrates a four-channel CD-FDM DDC front-end for the first time. The prototype was fabricated in a 180 nm BCD process, occupying a core area of 1.602 mm(2). The measurement shows a total harmonic distortion (THD) of 0.073% at a 260 mV(pp) input. The signal-to-noise-and-distortion ratio (SNDR) and dynamic range (DR) are 54.55 dB and 62.52 dB, respectively. The integrated noise from 0.5 Hz to 9.77 kHz is measured at 5.79 mu V-rms, corresponding to a 9.34 noise efficiency factor (NEF). The experimental results demonstrate it to be a promising candidate for multi-channel artifacts-tolerant front-ends with high compactness as well as high energy efficiency.

This article presents a fully integrated high-precision analog front end (AFE), consisting of a three-opamp instrumentation amplifier (IA) followed by a 24-bit Sigma Delta analog-to-digital converter ( Sigma Delta -ADC). Automatic-offset-calibration (AOC) and common-mode-cancellation (CMC) techniques are proposed to improve the measurement accuracy. The prototype has been fabricated in a 180-nm BCD process, which achieves an input offset of 40 mu V, an input impedance of 3.8 G Omega , and a common mode rejection ratio (CMRR) of 130 dB. The peak SNR and SNDR are 106.2 and 95.4 dB, respectively, while obtaining a dynamic range of 110.5 dB. In a three-lead resistance-temperature detector (RTD) temperature measurement experiment, the prototype achieves an accuracy of 0.03 degrees C within a temperature range of -40 degrees C to 160 degrees C, whereas in a full-bridge pressure measurement using strain gauges, the relative error ranges from -12.6 to 39.0 ppm. The experimental results demonstrate the potential capability of the prototype to be widely adopted in high-precision instrumentation measurement.

This article presents a high dynamic range (DR) direct conversion front-end (Direct-FE) IC enabling the wearable acquisition of weak bio-potentials superposed onto large motion artifacts (MAs). The prototype IC has been fabricated in a standard 0.18-mu m CMOS process. Benefiting from the proposed feedback (FB) two-step direct conversion architecture with an improved A-modulation, as well as a novel differential difference amplifier (DDA) and a dynamic-element-matching (DEM) technique, it achieves a peak input range of 3.56 V-pp, an input- referred noise (IRN) of 2.2 mu V-rms, an input impedance of 26 G Omega, and a +/- 1.8-V electrode de offset (EDO) tolerance, while consuming only 63-mu W power. Compared with state-of-the-art Direct FEs, the proposed work demonstrates an advanced DR (112 dB) and a competitive FOMDR (175 dB). The prototype IC has been validated based on in vivo experiments, demonstrating its capability for artifact-tolerant wearable bio-potential acquisition.

This brief proposes a high-linear transconductance cell based on parallel source degeneration and differential flipped voltage followers (FVFs) with balance resistors. The prototype is implemented in a 180 nm BCD process, occupying a core area of 0.0298 mm(2). Experimental result shows that the 1% total harmonic distortion (THD) linear input range is up to 480 mV(pp) with a 1.8 V voltage supply. The noise floor is 80.53 nV/root Hz, and the integrated noise is 8.69 mu V-rms within the bandwidth of 0.3-10 kHz. The proposed transconductance cell is applied to a multi-input sensor interface based on frequency division multiplexing (FDM), demonstrating its effectiveness and versatility in practical applications.

Advancements in integrated circuit (IC) technology have accelerated the miniaturization of body-worn sensors and systems, enabling long-term health monitoring. Wearable electrocardiogram (ECG), finger photoplethysmogram (PPG), and wrist-worn PPG have shown great success and significantly improved life quality. Chest-based PPG has the potential to extract multiple vital signs but requires ultra-high dynamic range (DR) IC to read out the small PPG signal among large respiration and artifacts inherent in daily life. This paper presents a dedicated high DR system for wearable chest PPG applications with a small form factor. The whole measurement system is integrated on a 20 cm2 PCB board. We have formulated a comprehensive evaluation protocol to validate the system with on-body chest PPG measurement in the workspace environment. First, chest PPG data was obtained from 6 adults and compared to data from a standard ECG patch. This system showed an average absolute deviation (AD) of 0.41 beats per minute, achieving > 99.53% heart rate (HR) accuracy. Second, chest PPG was recorded and compared to conventional PPG finger clip and PPG wristband, also showing > 98.6% HR matching and an absolute deviation in the standard deviation of NN intervals (SDNN) of <12.8 ms for HRV monitoring within the protocol. Moreover, it successfully derives other vital parameters such as respiration rate and blood oxygen level (SpO 2 ), showing the advancement among all these three reference modalities. This system can pave the way for new application areas, such as chest patches, to monitor chronic heart and respiratory diseases.

This article presents a 32-bit two-step incremental analog-to-digital converter (IADC) for non-invasive Brian-computer-interface (BCI). The prototype has been implemented with 180 nm BCD process at a supply voltage of 5V, including a low-noise front-end PGA followed by an IADC. The simulation results shows the IADC achieves a signal-to-noise ratio (SNR) of 124.9 dB and a dynamic range (DR) of 125.6 dB, while consuming 2.95 mW of power, leading to a competitive figure-of-merit (FoMS,DR) of 177.9 dB. The two-step architecture enables significant DR extension as well as power and area reduction, facilitating its widespread applications to multi-channel and high-accuracy wearable EEG acquisition with advanced tolerance to motion-artifacts.

Monitoring our multi-biological signals (bio-signals) provides us with a holistic view of our physiological condition (Figure 1). With increasing demand for integrating multiple bio-signals into a single chip, it is imperative to address multiple design challenges for efficient multi-modal biosensor acquisition [1]. The bio-signals include bio-potential signals (ExG), photo-plethysmography signals (PPG), and bio-impedance signals (BioZ) that are all unique in their electric properties (voltage, current, and resistance), have a large dynamic range ($4 \times$ order magnitudes in frequency and amplitude), and have a tremendous amount of variation among channels (middle of the Figure 1). The challenge of amplifying and quantizing diverse in-band bio-signals with a single signal acquisition circuit has attracted significant attention among researchers [2–6].

This paper proposes a high dynamic range 4(th)-order Delta-Sigma modulator (DSM) designed for column-parallel readout analog-to-digital converters (ADCs) in medical X-ray detectors. The design achieves improved power and area efficiency and better robustness against clock jitter and process mismatch by using a hybrid continuous-time (CT) and discrete-time (DT) loop filter structure. The adoption of non-delayed DT integrators stabilizes the system and expands the maximum stable amplitude (MSA) to up to 0.7 Vpp under a 1.8V power supply. The bandwidth of the proposed DSM is 24kHz. With the presence of process mismatch, the implemented DSM can still achieve a dynamic range (DR) of about 96dB with a 6.144MHz sampling rate. The power consumption of the DSM is estimated as around 486.5 mu W by using a standard 180-nm CMOS process.