Das österreichische Fachhochschulsystem ist im Vergleich zu anderen Ländern relativ jung und damit ist es nicht verwunderlich, dass Forschung und Entwicklung an österreichischen Fachhochschulen noch keine derart lange Tradition wie etwa an Universitäten vorweisen kann. Zudem ist die langfristige und nachhaltige Etablierung von thematischen Forschungsschwerpunkten, Know-how und Personal aufgrund der fehlenden Basisfinanzierung für F E trotz gesetzlich verankertem Forschungsauftrag nicht immer einfach. Ungeachtet dieser Umstände betreibt die Forschungsgruppe Embedded Systems der FH Technikum Wien seit nunmehr über 20 Jahren erfolgreich anwendungsnahe Forschung, über geförderte oder direkt von Industriepartnern beauftragte F E-Projekte, sowohl im Bereich der Hardware als auch der Software für eingebettete Computersysteme. So manches Mitglied im Team ist dabei ehemaliger Mitarbeiter des Instituts für Computertechnik der TU Wien, womit auch der Konnex zum Schwerpunkt dieser Ausgabe der Zeitschrift e+i hergestellt sei. Dieser Beitrag will die Entwicklung der Forschungsgruppe Embedded Systems an der FH Technikum Wien in ihrer Projekthistorie und ihren Themenschwerpunkten darstellen und schließlich auch einen kurzen Ausblick auf zukünftige Aktivitäten geben.

Field-Programmable Gate Arrays (FPGAs) can be found in an increasing number of application domains, such as the telecom industry, the automotive electronics sector, or automation technology as well as in the area of reconfigurable computing. In recent years, it can be observed that the open-source idea which is known from the software domain for a long time also became popular in the world of hardware and FPGA design. In the era of the Internet of Things, many of today's electronic devices implement some kind of network interface with Ethernet being known as one of the most widely used network standards. Thus, there is consequently a high demand on available Ethernet implementations for FPGA platforms. The goal of this work is to survey available open-source Ethernet MAC IP cores, evaluate existing designs in terms of performance, resource utilization, code quality, or maturity, and to present and summarize the evaluation results herein. Furthermore, advantages of commercial solutions and related publication work are discussed. To the authors' best knowledge, this is the first publication that evaluates and compares existing open-source Ethernet MAC IP cores on a large scale. This work should help designers to select an appropriate open-source Ethernet MAC for an FPGA design and shows possible pitfalls and things to pay attention when using an open-source IP core in general. Finally, the authors would like to show that the open-source community can be also very helpful in the world of hardware in terms of design reuse or time to market.

Integrated analog circuits that can be updated with respect to certain parameters in the field are not new and they are available on the market since many years. However, the production of many commercial solutions that appeared on the market in the last 2–3 decades has been discontinued and also existing literature is often outdated. We here thus want to give a summary of the technology with a focus on commercial devices that are available today, survey recent academic work including some historical aspects, and thereafter compare existing solutions in order to provide an overview on FPAA (Field Programmable Analog Array) technology which is up to date. A number of selected use cases will be presented and analyzed in order to assess possible advantages over e.g. discrete circuits.

Basic Linear Algebra Subprograms (BLAS) has emerged as a de-facto standard interface for libraries providing linear algebra functionality. The advent of powerful devices for Internet of Things (IoT) nodes enables the reuse of existing BLAS implementations in these systems. This calls for a discerning evaluation of the properties of these libraries on embedded processors. This work benchmarks and discusses the performance and memory consumption of a wide range of unmodified open-source BLAS libraries. In comparison to related (but partly outdated) publications this evaluation covers the largest set of open-source BLAS libraries, considers memory consumption as well and distinctively focuses on Linux-capable embedded platforms (an ARM-based SoC that contains an SIMD accelerator and one of the first commercial embedded systems based on the emerging RISC-V architecture). Results show that especially for matrix operations and larger problem sizes, optimized BLAS implementations allow for significant performance gains when compared to pure C implementations. Furthermore, the ARM platform outperforms the RISC-V incarnation in our selection of tests.

Since their introduction in the 1970s, Programmable Logic Devices (PLDs) evolved from implementing small glue-logic designs to large, configurable multi-processor Systems-on-Chip (SoC). Today's most prominent PLD technology, known as FPGA (Field-Programmable Gate Array), is used in an increasing number of application domains, such as the telecom industry, the automotive electronics sector or automation technology, and recent market studies expect a continuous demand for these sophisticated microelectronic devices in the future. For small and medium enterprises and/or SME-dominated countries like Austria, FPGAs can provide access to VLSI (Very Large Scale Integration) technology by avoiding the immense NRE (Non-Recurring Engineering) costs of ASICs (Application-Specific Integrated Circuits). This work outlines how today's and future electronic-based systems can benefit from FPGA technology. Trends, tools and design flows will be explained as well as research challenges that are currently investigated within two public funded R&D projects at the University of Applied Sciences Technikum Wien.

This work provides an overview of digital logic simulators which are the classical tools for verification of digital hardware. Existing simulators and their features are presented and both commercial simulators as well as tools from the open-source community are included in our survey. Furthermore, the tools have been evaluated using a set of benchmark designs. All of the evaluation designs are freely available over the internet and have been carefully selected so that everybody can prove the results presented herein. To the authors best knowledge this is the first public available overview on existing digital logic simulators since 20 years.

FPGAs are increasingly used in safety-critical applications (e.g., in aerospace and automotive engineering). Safety standards stipulate that implemented countermeasures against run-time faults such as detection and isolation of affected components, automatic reconfiguration, and redundancy mechanisms must be adequately verified. To that end, fault injection tests by various means have been established as a suitable method.For such tests, faults can be provoked by radiation, simulation, or manipulating the design, for example, by inserting additional logic or manipulating the synthesis flow. This work briefly summarizes the various fault injection approaches with a focus on methods that are capable of stressing critical nets of a design running on actual hardware without requiring to re-synthesize. While the state-of-the-art tools can work with complex designs, they often lack controllability of the exact timing of the injection events (which is important to track the system's response on faults in a logic simulation) and/or use a high amount of FPGA resources. To overcome these issues, we propose a resource-saving netlist-based fault injection framework Fault InJection Instrumenter (FIJI) that can target individual nets at test runtime. This paper presents FIJI's work flow, implementation details, and an evaluation in terms of FPGA resources, timing impact, and performance during instrumentation and test execution. The FIJI framework has been made publicly available by the authors under an open-source license.

Many emerging applications based on technologies like machine learning or cryptography mandate increased numerical computations being carried out close to the sensors in respective embedded processing units. Rather than reinventing the wheel, adoption of existing mathematical software libraries from standard desktop computing seems viable. To that end, this paper evaluates existing implementations of the Basic Linear Algebra Subprograms (BLAS) interface for their use on embedded computing devices. In particular, various implementations are benchmarked with regard to their performance and memory consumption on a comparatively small RISC CPU. To facilitate classfication on a broader range we use a diverse selection of test applications from small synthetic benchmarks like simple vector and matrix operations to real-world applications using Artificial Neural Networks (ANNs).

This work presents a proof-of-concept of a new approach on automatic generation of digital hardware that is able to check application -level properties of an embedded system such as a faulty system behavior at runtime. The approach makes use of assertion -based verification setups that today are very common in the area of digital hardware design with, however, the sole focus on logic simulation. Thus, a PSL-to-VHDL compiler is introduced that generates VHDL (Very High Speed Integrated Circuit Description Language) code out of PSL (Property Specification Language) assertions which can be further processed by a traditional digital logic synthesis tool. That way, runtime checker units can be automatically generated with little effort because of the already existing assertion -based test benches. Furthermore, a model railway demonstrator is presented herein as an example for a safety -critical application to prove the proposed tool flow on a use case. Implementation results based on that use case are discussed. Finally, the paper concludes with a brief outlook on related future work of the authors.

Advances in semiconductor miniaturization are an important driver for Field Programmable Gate Arrays (FPGAs) since their invention in the 1980s. The increasing number of available on chip logic resources on one hand and on the other hand a decrease in part costs let the FPGA market grow steadily in recent years. It comes thus at no surprise that more and more microprocessors are integrated into programmable logic devices as they represent the central functionality in many digital systems. In parallel to these technological developments the open-source hardware community grew steadily in the last two decades. More than hundred open-source CPU cores can thus be found and selecting a core for a design project has to be done with care. In this work we thus want to focus on open-source 32-bit CPU IP cores suitable for FPGAs and which support the upcoming free and open RISC-V instruction set architecture that has some interesting advantages when compared to commercial CPU cores (as will be outlined in the paper). An overview on available projects and activities will be given and evaluation results for a selection of cores will be presented.

High-Ievel synthesis promises a boost in productivity by enabling synthesis of low-level electronic circuit descriptions out of high-level source code. In this work-in-progress paper we present a preliminary evaluation of two freely available high-level synthesis tools using four case studies. We describe the steps required in order to obtain a synthesizable FPGA design from C source code for each use case and discuss the performance of the resulting hardware implementations.

This work presents a model railway based demonstrator for safety-critical applications. The demonstrator is intended as a use case for both R&D projects as well as educational activities of the authors in context to courses that are related to aspects of functional safety and fault-tolerant design. Furthermore, the demonstrator shall pose an attractive eye-catcher for public events of the University of Applied Sciences Technikum Wien. Both details of the demonstrator's design as well as implementation results including design decisions and requirements are presented herein. Possible application scenarios are outlined as well as already existing demonstrators that influenced the work of the authors. The paper concludes with an outlook of future activities that will rely on the demonstrator.

This work presents a demonstrator for safety-critical applications based on a low-cost FPGA platform. The main goal of the demonstrator is to show the features and benefits of a fault-injection tool for FPGAs called FIJI (Fault Injection Instrumenter) that was developed by the authors of this paper. Besides, the demonstrator should illustrate typical sources of hardware/software faults as well as approaches and methods for fault-tolerant design that are commonly applied to modern electronic based systems. Both details of the demonstrator's design as well as implementation results including the overhead on resources caused by the proposed fault-injection logic are presented. The demonstrator is portable to FPGA families of different FPGA vendors and can be implemented by using freeware/open-source design tools. Finally, it is planned that all design data of the demonstrator (including source code and documentation) will be available under an open-source license.

In this work we propose the rather new approach to synthesize properties formulated in verification languages, in particular PSL, down to hardware level. Such flow can be useful especially for safety-critical applications to automatically generate runtime monitors at little additional design efforts. Existing assertion synthesis tools from both academia and industry are presented as well as evaluation results concerning their features and drawbacks. The main part of this work focuses on the development of a proposed own tool flow which could benefit from available commercial and/or open-source tools like PSL parsers and equivalence checkers. The paper concludes with an outlook to future work in order to smoothly integrate our proposed approach into an existing state-of-the-art FPGA design flow. First resource estimations from previous work showed that optimized hardware assertion checkers may make up only a few percentage of the designs complete size.

Ao. Univ.-Prof. Dipl.-Ing. Dr. techn. Andreas Steininger Liebe Leserinnen und Leser, die Mikroelektronik ist zweifellos die Schlusseltechnologie unserer modernen Informationsgesellschaft. Viele alltagliche Dinge wie Smart Phones oder das Internet wurden in ihrer heutigen Form ohne die Errungenschaften der Mikroelektronik schlichtweg nicht existieren. In der Automobiltechnik geht ein Grosteil der Innovationen der letzten 20 bis 30 Jahre auf das Konto der Mikroelektronik, und auch in vielen anderen Applikationsbereichen wie der Medizintechnik, der Luftfahrt, der Industrieautomation oder der Konsumelektronik ist Mikroelektronik praktisch allgegenwartig. Naturlich werden Forschung und (Produkt-)Entwicklung in diesem wichtigen Bereich auch von osterreichischen Hochschulen und der in Osterreich ansassigen Industrie betrieben. Nun gilt Osterreich aber im Bereich der Hardwareentwicklung – und hier speziell auf Chip-Ebene – eher als Land der Analogtechnik, wahrend man mit der Entwicklung von digitaler Mikroelektronik gemeinhin vor allem geografische Regionen wie Asien oder die USA assoziiert. Dennoch gibt es in Osterreich auch im Bereich der digitalen Chips Aktivitaten und Produkte, die durchaus auf internationalem Niveau sind. Im Rahmen dieses Schwerpunktheftes soll daher nun der Fokus auf digitale Mikroelektronik in Osterreich sowie auf die in diesem Bereich tatigen Forschungsinstitutionen und Industriebetriebe gelegt werden. Die insgesamt acht Beitrage dieser ei selbst Verbindungsleitungen bedurfen komplexer Modelle und weisen subtile Fehlermodi auf. Damit ergeben sich entsprechende Herausforderungen zur Beherrschung der Komplexitat bei Entwicklung und in Folge auch Verifikation und Test derartig hochintegrierter Schaltungen. Dieses Themas nimmt sich beispielsweise ein in diesem Heft enthaltener Beitrag an, der uber einen von der FH Technikum Wien in Kooperation mit Infineon Technologies Austria entwickelten Verifikations-Ansatz berichtet, um die Brucke zwischen Pre-Silicon und Post-Silicon Verification von komplexen Mixed-Signal Systemon-Chip Designs zu schliesen. Ein bereits langer bekanntes Problem ist die stetige Zunahme der Leitungslangen am Chip – ein weiteres Resultat der Komplexitat heutiger VLSI-Designs. Sie macht die Einhaltung der Zielvorgaben fur das Timing immer schwieriger. Langst hat hier das WasserfallModell mit seiner strikten Trennung von Frontendund BackendDesign ausgedient, und eine Logiksynthese ist ohne Kenntnisse uber die physikalische Platzierung des Designs ineffizient. Bei komplexen VLSI-Chips mussen Timing-Aspekte zudem bereits beim Systemdesign, durch Anwendung von Paradigmen wie GALS (Globally Asynchronous, Locally Synchronous), berucksichtigt werden. In Zukunft werden in diesem Kontext zunehmend innovative Losungen zur OnChip-Kommunikation gefragt sein, wie beispielsweise Network-onChip-Architekturen, die auch in einem hier enthalten Beitrag der TU Wien zur Sprache kommen. Bezuglich der heutzutage ublichen Taktund Signalfrequenzen sind, getrieben durch den Einsatz von HighSpeed-Schnittstellen wie GBit-Ethernet, USB 3.x oder SATA, auch Chip-extern Frequenzen von zig GHz nicht unublich, womit man langst im HF-Bereich angelangt ist. Dies schafft, in Kombination mit dem hohen Pin-Count moderner VLSI-Chips (etwa sind bei aktuellen Hi-End FPGA-Bausteinen 1.000 Gehausepins und mehr keine Seltenheit), wiederum entsprechende Aufwande bezuglich des Board Designs. Eine weitere Folge der extremen Miniaturisierung der Transistorgeometrien in modernen Prozesstechnologien ist die zunehmende Anfalligkeit fur Fehler, wie zum Beispiel durch ionisierende Partikel hervorgerufene „Single Event Upsets“. Sie ist bedingt durch kleinere Spannungshube, kleinere kritische Ladungsmengen, hohere Taktfre-

A fault-injection tool can be very interesting in context to safety-critical applications, e.g., to test fault-detection and avoidance mechanisms or simply to stress an application and analyze its behavior when faults occur. In this work, a fault-injection tool is presented which can be used to instrument an FPGA design with fault-injection logic on netlist level during the implementation phase and to inject faults during runtime afterwards. The proposed approach can be smoothly integrated into an industrial FPGA tool flow, supports devices from multiple FPGA vendors and is highly configurable in order to fit to the number of available FPGA logic resources. Differences to related approaches which are applied on either HDL- and netlist-level as well as on the FPGA configuration bitstream are described. Finally, some results are presented to prove the applicability of the proposed solution.

In the area of ASIC design a stringent design and verification methodology is required to avoid bugs and safe time. This is also important when teaching such topics. In this work an overview on existing literature, tools and manufacturing options for digital ASICs with respect to education at the university level is given. Moreover, approaches, course material, prototype samples and infrastructure that have been developed at the University of Applied Sciences Technikum Wien to foster education in the area of ASIC design are described. That way, students are supported in designing their own ASICs at low efforts and costs. The proposed approaches could be interesting for other universities or research institutions working in the area of digital ASIC design.

This work investigates how assertion-based verification methods applied to simulations can also be used at application runtime. Such approach can be useful to speed-up verification as well as to implement hardware runtime monitors with respect to safety-critical applications. Existing tools and other related work are presented as well as two use cases which have been developed to benchmark the different approaches. The applicability of such flows in real-world applications is discussed, as well as possible traps and pitfalls when generating hardware out of hardware assertion languages. Finally, an outlook to future work based on the current results is given.

This work describes the prototype implementation of a sound generator for an electric quad bike. The main benefits of the proposed 8-bit microcontroller-based solution are little design efforts and low costs when compared to commercial available solutions. Details of the hardware and software parts of the sound generator are presented. Finally, some results of the prototype implementation are outlined in this paper.