Advanced metal-oxide-semiconductor field effect transistors, MOSFETs, have shown increasing sensitivity to microelectronic reliability based degradation phenomena and in particular, to negative bias temperature instability, NBTI. Previously [1] we have reported on a methodology to extract three distinct components of NBTI; recoverable charge, RC (oxide traps which discharge once the gate bias is zero), field recoverable charge, FRC (switching traps which seemingly discharged under positive gate bias), and interface state charge, IS (associated with the breaking of silicon-hydrogen bonds at the interface and do not discharge in an experimental time frame for temperatures below 180° C). Here we will report new results for NBTI for different oxide types and thicknesses and we will expand the methodology to include positive bias temperature instability, PBTI, oxide charging caused by the application of large positive biases. Both NBTI and PBTI will be examined for both p-channel and n-channel MOSFETS for each oxide type and thickness, which requires the measurement to be made in both accumulation and inversion modes. NBTI “Pseudo DC” measurements using the methodology discussed previously [1] have been made at 120° C on p-channel and n-channel MOSFETs to extract the three components of BTI after 1500 s of stress. The stressing bias was chosen so that |Vgs,stress|/tox = 3.25 V/3.4nm in order to keep the approximately the same fields. Measurements of the source – drain current, Ids, were made in the linear regime and the measured Ids variations with stress were converted into threshold voltage shifts, DVth [1]. Measurements were performed on devices fabricated using an IBM proprietary process with gate widths of 5 mm and gate length/oxide thicknesses of 130 nm/3.4nm, 240 nm/6.2 nm, 90 nm/2.4 nm, and 240 nm/6.2 nm (processed with 90 nm technology) with a oxynitride gate. Measurements were also performed on HP devices with gate widths of 10 mm, gate lengths ranging from 350-500 nm and a Si02 oxide thickness of 7 nm. It is worth noting that the sign of the trapped charges of each type depends upon the component being measured. In the case of IS, the sign of the charge can be inferred from the mechanism since dangling bonds are amphoteric. They will take on a charge based on the measurement Vgs, and thus for PMOS devices, the IS have positive trapped charge (negative voltage shift) whilst for NMOS the IS are negatively charged (positive voltage shift). The FRC charge component is always charged by holes and the RC charge is positive (negative voltage shift) except for PBTI in an NMOS. A sample table for the 130nm/3.4nm oxynitrided gate is shown below. The existence of positive charge injection, for a PMOS under PBTI can be explained by realizing that PMOS devices usually have a p-type polysilicon gate electrode. When a positive gate bias is applied, electrons will be drawn to the interface between the gate oxide and the substrate; thus there are no holes present to tunnel into the oxide; however, the same field will drive holes from the poly silicon/oxide interface and this is where the positive charge is coming from under these circumstances. A more puzzling result is that an NMOS under PBTI shows IS creation. Standard models of IS creation involve positive charge which either directly or through a complex process breaks the Si-H bond. These holes can come from the substrate for NBTI, or the polysilicon gate for a PMOS in accumulation, but the mechanism of hole injection for an NMOS undergoing PBTI is unclear. [1] C. Mayberry, D. D. Nguyen, C. Kouhestani, K. E. Kambour, H. P. Hjalmarson and R. A. B. Devine, “Measurement and Identification of Three Contributing Charge Terms in Negative Bias Temperature Instability,” ECS Trans., 50 (4), 223-232 (2012). Acknowledgements D. D. Nguyen and C. Kouhestani are with COSMIAC Kirtland, AFB, New Mexico USA 87117. This material is based on research sponsored by Air Force Research Laboratory (AFRL) under agreement number FA9453-08-2-0259. The U.S. Government is authorized to reproduce and distribute reprints for Governmental purposes notwithstanding any copyright notation thereon. The work performed by K. E. K. was supported by the US Air Force under contract FA9453-08-C-0245 sponsored, monitored, and managed by: United States Air Force Air Force Material Command, Air Force Research Laboratory, Space Vehicles Directorate, Kirtland AFB, NM 87117-5776. Table 1 A matrix showing the threshold voltage shift for the various BTI components and type of charge trapped by each component.

The existence of multiple, physically distinct components of Negative Bias Temperature Instability requires a measurement methodology which allows the extraction of each component independently. In this paper we present results obtained at room temperature, which minimizes both the interface state and switching trap components, allowing us to explore the trapping of holes at preexisting defects in the oxide. This is done for both SiON and HfO2/SiO2 oxide stacks of similar total thickness. Results are presented for both pseudo-DC and pulse stressing including the dependence of the pulse measurements on duty cycle. A two trap model using the Tewksbury formalism is proposed to predict the results.

The generation of interface states created by depassivating dangling bonds at the interface between the gate dielectric and silicon substrate is important for both the growth of Negative Bias Temperature Instability threshold voltage shift in MOSFETs and the radiation sensitivity of the devices. In this paper we present results comparing the generation of interface states for both processes and their possible annealing at high temperatures.

We have studied defect charging and discharging resulting from negative bias temperature instability in nitrided SiO2 gate insulator field effect transistors. Using pseudo-DC and pulsed stressing methods, we are able to extract at least three individual components associated with a) interface states at the semiconductor/insulator boundary, b) dynamically recoverable positive charging in the "bulk" of the insulator, and c) positive charge in the insulator which can be "eliminated" by application of a positive electric field across the insulator. It is argued that the charge variation in c) in fact arises via a charge neutralization process involving electron capture at switching traps and that this process can be simply reversed using a small negative field. The important role played by neutral oxygen vacancies (O-3 Si-Si O-3) and/or their variants involving partial N substitutions is emphasized. (c) 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim

We have performed negative bias instability (NBTI) measurements on 130 nm channel length Si MOSFETs with SiON gate dielectrics at different temperatures up to 220 °C. Using a pulsed stressiing and pseudo-DC measurements we have focused on the charging and annealing kinetics of only the interface state related component. At temperatures > 180 °C we find clear evidence for a diminution of the growth kinetics suggesting the onset of an annealing effect during interface state generation. We contrast the NBTI data with interface state growth in devices exposed to ionizing radiation. Possible physical mechanisms contributing to the “annealing” effect are discussed and associated with diffusing H2 molecules present in the substrate/gate insulator/polycrystalline Si gate structure.

This paper reports new high temperature measurements of Negative Bias Temperature Instability induced interface states in both NMOS and PMOS devices. Evidence of annealing of the interface states, previously thought to be “permanent”, is presented for measurements including a methodology which allows the direct measurement of the time dependent growth/recovery of the interface state component.

The equivalent role of hydrogen cracking in radiation effects and Negative Bias Temperature Instability (NBTI) is described. A prediction concerning thickness dependence is compared with data. The temperature dependence of interface trap density is explained.

The increase in the magnitude of the threshold voltage of a positive-channel metal oxide semiconductor (PMOS) under negative gate biasing (negative bias temperature instability) is attributed to the build-up of charge in the gate insulator. We have studied the charging and discharging of nitrided SiO2 gate insulator field effect transistors and through the use of pseudo-DC and pulsed stressing methods, have extracted, at least, three charging components. These components are (a) the charging of interface states at the semiconductor/insulator boundary, (b) dynamically recoverable positive charging in the "bulk" of the insulator, and (c) positive charging in the insulator, which can be "eliminated" only by application of a positive electric field across the insulator. It is proposed that the charge "elimination" in (c) arises via a charge neutralization process involving electron capture at switching traps, as opposed to de-trapping, and that this can be reversed by the application of a small negative field.

One of the most important requirements for modeling of the long-term effects of negative bias temperature instability (NBTI) on device/circuit response is an understanding of how to include the effect of duty cycle on the threshold voltage shift. Since NBTI is known to be comprised of both permanent and recoverable components, a measurement protocol must be established enabling separation of these components and then their recombination to predict the shift for different duty cycles. In the work reported here, we have endeavored to address these issues by combining pulsed and pseudo-DC stressing/relaxation methods.

Negative bias temperature instability has been studied in 130 nm and 90 nm channel length, SiO2 gate insulator field effect transistors at room temperature. Pulsed voltage stressing and subsequent recovery using times starting in the tens of microsecond regime were employed together with a single point data acquisition time ∼4 μs. Threshold voltage shifts were characteristic of oxide charge trapping as opposed to interface state generation. Recovery of the threshold voltage was modeled assuming quantum mechanical tunneling of trapped charges from the dielectric to the Si substrate.

In this work we show that annealing of silicon/silicon-dioxide/silicon structures in forming gas (N2:H2; 95:5) above 500°C leads to spontaneous incorporation of mobile H+ ions in the buried SiO2 layer. We demonstrate that, unlike the alkali ions feared as killer contaminants in the early days, the space charge distribution of these mobile protons within the buried oxide layer can be very well controlled and easily rearranged with relatively high speed at room temperature. The hysteresis in the flat band voltage shift provides a unique vehicle to study proton kinetics in silicon dioxide thin films. It is further shown how this effect has great potential as the basis for a reliable nonvolatile FET memory device that is expected to be competitive with state-of-the-art Si-based memory technologies. The power of this novel device is its simplicity; it requires few processing steps, all of which are standard in Si integrated-circuit fabrication.

We have performed electron spin resonance and electrical measurements on SiO2/Si structures subjected to anneals in 5% H2/N2 or 5% D2/N2 gases and subsequently injected with electrons using corona ions and ultra-violet radiation. Threshold voltage and transconductance measurements have also been made on 0.25 μm metal-oxide-semiconductor transistors subjected to 400 °C anneals in the same gases and subsequently aged by hot electron injection. The electrical data on SiO2/Si structures indicates that the density of interface states increases as a result of electron injection but that there are only minor differences between H and D passivated interfaces. The data on Pb, trivalent Si dangling bond, centers at the same interfaces observed by electron spin resonance is insufficiently accurate to enable us to observe any significant differences. The hot electron injection experiments on transistors, consistent with other authors, indicate that, for the limited number of measurements we have made, the transistor ageing resulting from the generation of interface states is significantly reduced for devices annealed in the D containing gas as compared to those annealed in the H containing gas. The origins of some potential differences in annealing behaviour between the SiO2/Si structures and the 0.25 μm transistors are suggested.

Negative bias temperature instability (NBTI) is an issue of critical importance as the space electronics industry evolves because it may dominate the reliability lifetime of space based assets. Understanding its physical origin is therefore essential in determining how best to search for methods of mitigation. It has been suggested ¬that the magnitude of the effect is strongly dependent on circuit operation conditions (static or dynamic modes). In the present work, we examine the time constants related to the charging and recovery of trapped charged induced by NBTI in HfSiON and SiO2 gate dielectric devices at room temperature.

Ever since the introduction of the metal-oxide-silicon field-effect-transistor (MOSFET), the nature of mobile and trapped charge in the oxide layer has been studied in great detail. For example, contamination with alkali ions such as sodium, causing instability of the flat-band voltage, was a major concern in the early days of MOS fabrication. Another SiO2 impurity of particular interest is hydrogen, because of its beneficial property of passivating charge traps. In this work we show that annealing of Si/SiO2/Si structures in forming gas (Ar:H2; 95:5) above 400 °C can introduce mobile H+ ions into the SiO2 layer. These mobile protons are confined within the oxide layer, and their space-charge distribution is well controllable and easily rearrangeable by applying a gate bias, making them potentially useful for application in a reliable nonvolatile MOSFET memory device. We present speed, retention, endurance, and radiation tolerance data showing that this non-volatile memory technology can be competitive with existing Si-based non-volatile memory technologies such as Flash. The chemical kinetics of mobile-proton reactions in the SiO2 film are also analyzed in greater detail. Our data show that the initial buildup of mobile protons during hydrogen annealing is limited by the rate of lateral hydrogen diffusion into the buried SiO2 films. The final density of mobile protons is determined by the cooling rate which terminates the annealing process and, in the case of subsequent anneals, by the temperature of the final anneal. To explain the observations, we propose a dynamical equilibrium model. Based on these insights, the incorporation of the proton generation process into standard semiconductor process flows is discussed.

We find that changes in threshold voltage induced by negative bias temperature stressing of p-channel field effect transistors with HfSiON gate dielectrics are modulated by the drain voltage, in measurements wherein the drain current is measured during stressing. This effect is not observed in SiO2 gate devices. Short channel effects are excluded as explanations, leading us to conclude that positive charge in the dielectric stack is laterally mobile and is conducted out of the insulator via the drain. Further, a simple qualitative model of charging kinetics allows us to extract the density of interface states as a function of time, and shows that these defects build in time, reaching numbers on the order of 1011cm−2 after hundreds of seconds.

Ultraviolet radiation has been used to anneal out extrinsic defects in several types of deposited a-SiO2 films. The UV light was obtained from a new krypton UV-VIS-IR lamp with a spectral range of 170 nm < λ, < 3 μm. This “cold” annealing was performed on a-SiO2 films with various thicknesses up to 400 nm. The films were deposited by various techniques, ultraviolet induced chemical vapour deposition (UVCVD), plasma enhanced vapour deposition (PECVD) and spin-on-glass (SOG). Fourier Transform Infra-Red spectroscopy (FTIR) and Electron Spin Resonance (ESR) were used to characterize the effect of the radiation. In the case of UVCVD and SOG a-SiO2 films, it is shown that the UV radiation removes the Si-H bonds and reduces significantly the amount of C-H and C-H3 groups. In both these films, an important reduction in the amount of adsorbed water and Si-OH groups is observed, together with an increase in the number of Si-O bonds. In PECVD films made with tetraethylorthosilicate (TEOS) vapour and O2 as precursor gases, we find evidence for an important reduction in the amount of C and the number of CnHy related defects. The UV treatment is effective even at temperatures as low as 100 °C, which suggests that it could constitute a much needed low temperature annealing step.

Electron spin resonance measurements have been carried out on samples of Suprasil Wl (dry silica) subjected to ultraviolet laser radiation (λ = 248 nm, E = 5 eV/photon). Studies have been made for fixed irradiation temperature (room) variable accumulated ultraviolet dose and fixed accumulated dose (3000 J/cm2) at various irradiation temperatures in the range 110 K to 335 K. Three principal defect centers are observed. Non-bridging oxygen hole centers are created at all temperatures in the range studied with slightly higher efficiency at room temperature (ration 300 K/150 K ∼ 2.5). Comparison of the dose dependent growth curve of the 4.8 eV absorption and its isochronal annealing curve with those for the oxygen hole center clearly identify the origin of the absorption band with this defect. A threshold temperature ∼ 200 K is found for oxygen vacancy creation consistent with results on single crystalline quartz. Post irradiation annealing at 593 K eliminates the vacancy centers and the peroxy radical resonance appears. Its growth as a function of accumulated ultraviolet dose and irradiation temperature supports the hypothesis that peroxy radicals form by the trapping of diffusing, molecular oxygen at the oxygen vacancy center.

We present negative bias temperature instability (NBTI) charge stress data, taken on 1 um HfSiON MOSFETs, which suggests the existence of an NBTI relaxation mechanism not previously reported in the literature. In particular, we observe significantly less NBTI damage in devices stressed in the MOSFET saturation region (large Vds) than in those stressed in the linear region (small Vds). We propose that this observation is explained by transport of trapped positive charge parallel to the channel, but inside the insulator, perhaps along a high defect density region in the HfSiON. This observation has interesting and important implications for high-k materials studies and NBTI measurement protocols.