An ECL (emitter coupled logic) circuit with an AC-coupled active pull-down emitter follower configuration is described. An unloaded ring oscillator gate delay of 13.2 ps has been achieved at 6.2 mW, in a 50 GHz-fT ion-implanted silicon bipolar technology. This circuit could be useful as an internal gate operating at low-power and as an I/O gate to drive a large capacitive load at high-power. In both cases, this circuit offers superior power-delay performance compared to conventional ECL circuits

The authors present a single-poly bipolar technology using an advanced transistor with an LDD (lightly doped drain)-like self-aligned lateral profile. The device is isolated by a silicon-filled deep trench with a collector-to-collector breakdown voltage of 33 V, and the field oxide is provided by a low-temperature breakless process. The integrated process yields a structure with minimal topography, thereby avoiding several serious concerns associated with the conventional double-poly structures. Using this technology, sub-50-ps ECL (emitter coupled logic) circuits have been realized, demonstrating for the first time the potential of the single-poly device.<>