The rapid growth of computing demands driven by scientific computing, data analytics, and artificial intelligence (AI) advancements has exposed the limitations of traditional digital processing systems. These systems are nearing physical energy barriers, making significant gains in energy efficiency increasingly unattainable. As we advance toward post-exascale computing, disruptive approaches are critical to overcoming these limitations. Among emerging analog solutions, biochemical computing offers a transformative path for achieving orders-of-magnitude improvements in energy efficiency. By leveraging the natural optimization capabilities of chemical reaction networks (CRNs), biochemical systems have the potential to meet high-performance computing needs through natural scalability. However, numerous challenges remain, including theoretical limitations in mapping computational problems to CRNs and practical barriers in implementing biochemical computing devices. In this paper, we present a framework for chemical computation using biochemical systems and introduce key components of our approach for energy-efficient scientific computing. We showcase the feasibility of this framework by solving a system of ordinary differential equations by emulating a chemical reservoir device, demonstrating its potential for addressing modern computing challenges. This work lays a foundational step toward harnessing the computational power of chemistry to design energy-efficient, scalable, high-performance next-generation computing systems.

Transformer blocks are prevalent in large language model (LLM) but present deployment challenges due to their challenging computational and memory demands. While prior work has typically optimized attention mechanisms or feed-forward networks (FFNs) separately, few hardware (HW) architecture have jointly addressed both components with co-designed hardware acceleration. We present ELiTeFormer (Efficient Linear Ternary Transformer), the first Transformer model architecture that unifies hybrid linear attention with ultra-low-precision (ternary) linear projections, specifically co-designed for field-programmable gate array (FPGA) deployment. ELiTeFormer achieves 10x model weight compression and 12.8x key-value (KV) cache compression compared to LLaMA 3, while maintaining competitive accuracy (31.9

High-Level Synthesis (HLS) has democratised Field-Programmable Gate Array (FPGA) programming, yet Dynamic Partial Reconfiguration (DPR)—which enables runtime logic swapping for adaptive or oversized workloads—remains manual and expert-only. HiPR [1] adds limited compiler support but restricts modules to one-to-one region mappings without runtime management. MLIR-DPR introduces: (i) a dpr dialect in the Multi-Level Intermediate Representation (MLIR) infrastructure [2] for identifying mutually exclusive regions; (ii) automated interface synthesis, floorplanning, and multi-threaded scheduler generation; and (iii) demonstrated Software-Defined Radio (SDR), Design-Space Exploration (DSE), and virtual-area applications.

As custom hardware accelerators become increasingly central to machine learning workloads, efficient data transfer is critical for maximizing accelerator performance on linear algebra kernels. AXI4MLIR, an extension of the Multi-Level Intermediate Representation (MLIR) compiler framework for automated generation of host-accelerator driver code, incurs significant runtime overhead due to non-zero-copy CPU-accelerator data movement. During transfers from the host to the accelerator, data is copied from heap-allocated memory buffers into contiguous Direct Memory Access (DMA)-mapped buffers. This work identifies this copy as a redundant staging operation and eliminates it through zero-copy data movement. The optimization extends accel, an MLIR dialect introduced by AXI4MLIR, and implements lowering support that allocates buffers directly within DMA-mapped memory, thereby omitting the staging copy. We evaluate the proposed scheme using a configurable matrix-matrix multiplication accelerator and show that the zero-copy optimization reduces main memory data movement by up to 2x, increasing overall accelerator utilization.

The next generation of particle physics experiments will face a new era of challenges in data acquisition, due to unprecedented data rates and volumes along with extreme environments and operational constraints. Harnessing this data for scientific discovery demands real-time inference and decision-making, intelligent data reduction, and efficient processing architectures beyond current capabilities. Crucial to the success of this experimental paradigm are several emerging technologies, such as artificial intelligence and machine learning (AI/ML), silicon microelectronics, and the advent of quantum algorithms and processing. Their intersection includes areas of research such as low-power and low-latency devices for edge computing, heterogeneous accelerator systems, reconfigurable hardware, novel codesign and synthesis strategies, readout for cryogenic or high-radiation environments, and analog computing. This white paper presents a community-driven vision to identify and prioritize research and development opportunities in hardware-based ML systems and corresponding physics applications, contributing towards a successful transition to the new data frontier of fundamental science.

We present an MLIR flow that partitions neural networks and schedules them as software-driven macro-dataflow pipelines for low-latency streaming on CPU-FPGA SoCs. A new dataflow dialect and token-based scheduler pipeline even cyclic graphs with external memory, overcoming HLS limits. On an AlphaData ADM-PA101 (Versal VM1802) we demonstrate low-latency streaming; to our knowledge this is the first HLS flow to pipeline cyclic NN graphs.

The widespread adoption of energy-intensive computing applications has led to a growing need for energy-efficient computing approaches. Thermodynamic computing offers a promising approach for low-energy computation by leveraging the intrinsic computational capabilities of physical, chemical, or biological systems. However, the mathematical foundations of thermodynamic computing require further development to fully realize the potential energy efficiencies, as well as to assess factors like noise and operational speed. In this paper, we establish a mathematical framework for utilizing thermodynamic processes to perform fundamental operations, including addition, subtraction, multiplication, and division. We highlight the use of chemical reactions as potential computational units and explore synthetic chemical and biochemical systems as practical implementations. Additionally, we demonstrate how these principles can be applied to solving complex mathematical problems, such as ordinary differential equations (ODEs) and suggest the necessary components to implement the thermodynamic computing framework using chemical reactions based in a microfluidic device. This work enhances our understanding of thermodynamic processes for natural computing as a basis for scalable, energy-efficient computation in paradigm disruptive next-generation systems.

The escalating performance demands of modern applications are driving the High-Performance Computing (HPC) industry toward massive, heterogeneous systems designed to tackle increasingly diverse workloads. As these architectures evolve to incorporate specialized accelerators like GPUs, the underlying software stack has become fragmented and complex, significantly burdening the development of distributed applications. In this work, we present a methodology designed to streamline the deployment of high-performance applications on HPC clusters while fully exploiting their heterogeneous compute capabilities. We advocate adopting standard programming interfaces, specifically the C++ Standard Template Library (STL), extended via specialization to support transparently distributed and accelerated execution. Our approach retains flexibility, allowing developers to integrate accelerator-specific languages and frameworks for fine-grained optimization or ecosystem compatibility. To validate our methodology, we present a case study in the life sciences domain: a high-performance, distributed implementation of the Smith-Waterman algorithm. Running on a heterogeneous GPU-accelerated cluster, our solution achieves a performance improvement of up to 5.88× over the current state of the art.

Ensuring power grid resiliency, forecasting climate conditions, and optimization of transportation infrastructure are some of the many application areas where data is collected in both space and time. Spatiotemporal modeling is about modeling those patterns for forecasting future trends and carrying out critical decision-making by leveraging machine learning/deep learning. Once trained offline, field deployment of trained models for near real-time inference could be challenging because performance can vary significantly depending on the environment, available compute resources and tolerance to ambiguity in results. Users deploying spatiotemporal models for solving complex problems can benefit from analytical studies considering a plethora of system adaptations to understand the associated performance-quality trade-offs.To facilitate the co-design of next-generation hardware architectures for field deployment of trained models, it is critical to characterize the workloads of these deep learning (DL) applications during inference and assess their computational patterns at different levels of the execution stack. In this paper, we develop several variants of deep learning applications that use spatiotemporal data from dynamical systems. We study the associated computational patterns for inference workloads at different levels, considering relevant models (Long short-term Memory, Convolutional Neural Network and Spatio-Temporal Graph Convolution Network), DL frameworks (Tensorflow and PyTorch), precision (FP16, FP32, AMP, INT16 and INT8), inference runtime (ONNX and AI Template), post-training quantization (TensorRT) and platforms (Nvidia DGX A100 and Sambanova SN10 RDU).Overall, our findings indicate that although there is potential in mixed-precision models and post-training quantization for spatiotemporal modeling, extracting efficiency from contemporary GPU systems might be challenging. Instead, co-designing custom accelerators by leveraging optimized High Level Synthesis frameworks (such as SODA High-Level Synthesizer for customized FPGA/ASIC targets) can make workload-specific adjustments to enhance the efficiency.

In-situ Electron Energy Loss Spectroscopy (EELS) is a crucial technique for determining the elemental composition of materials through EELS Spectrum Images (EELS-SI). While recent innovations have made it possible for EELS-SI data acquisition at rates of 400 frames per second with near-zero read noise, the challenge lies in processing this massive stream of real-time data to capture nanoscale dynamic changes. This task demands advanced machine learning methods capable of identifying subtle and complex features in EELS spectra. Furthermore, the EELS data acquired in difficult experimental conditions often suffer from a low signal-to-noise ratio (SNR), leading to unreliable classification and limiting their utility. In response to this critical need, we introduce a spiking neural network (SNN)-based Variational Autoencoder (VAE) that embeds spectral data into a latent space, facilitating precise prediction of structural changes. VAEs are designed to learn efficient low-dimensional representations while capturing the inherent variability in the data, making them highly effective for processing multidimensional data. Additionally, SNNs, which use biological neurons, offer unmatched scalability and energy efficiency by processing information through binary spikes, making them ideal for high-throughput data. We validate our framework using MXene annealing data, achieving denoised spectrum images with an SNR of 28.3dB. For the first time, we present a fully online learning solution for dynamic structural tracking, implemented directly in hardware, eliminating the traditional bottleneck of offline training. Our method achieves reliable, real-time, on-device characterization of high-speed EELS data when evaluated on an FPGA platform. Joint experiments with the SNN-VAE model on both spiking autoencoder hardware and a softwaretrained hybrid configuration of hardware spiking encoders demonstrated latency reductions of 25.2x, 93.7x, and 1.04x, 4.5x in energy savings, respectively, compared to baseline.

Software Defined Accelerators (SODA) [1] is an automatic and agile framework to streamline the synthesis of deep neural network (DNN) models into hardware descriptions from their high-level programming environment (e.g., PyTorch) by leveraging Multi-Level Intermediate Representation (MLIR) compiler infrastructure and High-Level Synthesis (HLS) techniques. This work focuses on improving both the design quality and turnaround time of the SODA framework via exploring optimizations such as loop transformations and memory optimizations to enable practical DNN accelerator synthesis. In particular, we propose ML4SODA, a machine learning (ML) based Design Space Exploration (DSE) engine that systematically evaluates HLS optimizations across different DNN model layer types. ML4SODA incorporates a Decision Tree, which is trained from prior HLS runs, and during inference, it directly generates the optimal HLS parameters for SODA to achieve performance-optimal or energy-efficiency-optimal design points. Built into SODA's compilation passes, ML4SODA demonstrate both faster synthesis time and high quality designs on large DNNs.

Transformer-based large language models (LLMs) have exploded in popularity in both industrial and academic settings, seeing rapid progress in model quality over the last few years and unprecedented levels of adoption worldwide. Acceleration of these transformer architectures and their efficient alternatives [1], [2] has surged in relevance to meet the aforementioned efficiency needs. Field programmable gate arrays (FPGAs) provide the ability to implement highly specialized accelerators for these transformer architectures. Recent work [3], [4] has demonstrated benefits but also unique challenges posed by FPGA-based solutions. We posit existing FPGA solutions are attempting to accelerate an algorithm that is ultimately a poor fit, resulting in avoidable inefficiencies. We address this with our proposed ultra-efficient architecture UltraFormer and design it with the challenges facing FPGA acceleration solutions in mind. This work makes a number of critical contributions: •We propose an efficient transformer architecture featuring the first-ever combination of hybrid linear attention and extremely low-precision linear projections. These features contribute to ~10x compression of the model weights and 13.2x key-value (KV) cache compression in long-context scenarios compared to Llama3 architectures. •We synthesize, simulate, and deploy UltraFormer via HLS flows [5] targeting enterprise-level Xilinx FPGAs. This represents the first time that an efficient attention mechanism featuring linear attention has been synthesized for FPGA deployment and the first time that BitNet b1.58 linear projections [6] have been synthesized or simulated for custom hardware. •We demonstrate that UltraFormer produces notable throughput and energy efficiency improvements. When deploying UltraFormer on a Xilinx VCK5000, we see up ro a 4.4x reduction in latency and a 3.2x reduction in power consumption compared to Llama3 running on a NVIDIA A100 GPU.

Domain-specific systems improve the performance of specific applications compared to general-purpose processing systems by deploying custom hardware accelerators. These hardware accelerators are generated using high-level synthesis (HLS) tools. The HLS tools enable a comprehensive design space exploration, optimizing the accelerators' compute performance. However, they often ignore the challenges of implementing the accelerators in a system-on-chip, particularly how they access memory. Our work introduces a buffering system design that improves accelerators' memory accesses by intelligently employing burst transactions to prefetch useful data from external memory to on-chip local buffers. Our design is dynamic, parametric, and transparent to the accelerators generated by HLS tools. We derive the buffering system parameters using appropriate compiler-based analysis passes and memory channel latency constraints. The proposed buffering system design results in, on average, 8.8x performance improvements while lowering memory channel utilization by 53.2% for a set of PolyBench kernels.

In this paper, we describe the two new U.S. DOE projects that address lowering the cost of hardware R&D and reducing the time and effort required to develop specialized hardware for novel algorithms. These projects support DOE goals for energy-efficient computing with new heterogeneous computing paradigms and edge computing integrated with instrumentation and sensors. These projects are part of the DOE contributions to the U.S. CHIPS and Science Act that was launched in 2022. These projects are also examples of interagency alignment where DOE will develop designs and supporting software that will target significant microelectronics hardware prototyping and packaging capabilities from the U.S. DOC.

The acceleration of scientific computation, data analytics, and artificial intelligence is driving a surge in computational requirements. Yet, state-of-the-art high-performance computing systems are approaching physical limitations that impede further significant improvements in energy efficiency. As we move towards post-exascale computing systems, innovative approaches are necessary to overcome this barrier in power consumption. Novel analog and hybrid digital-analog architectures hold promise for enhancing energy efficiency by several orders of magnitude. Biochemical computation stands out among the various solutions being explored due to its potential to enable new classes of devices with immense computational capabilities. These devices can capitalize on the inherent efficacy of biological cells in solving optimization problems and are scalable through increasing reaction system size or vessel capacity, potentially satisfying scientific computing's high-performance requirements. Nonetheless, several theoretical and practical limitations persist, including problem formulation and mapping to chemical reaction networks (CRNs) and implementation of actual CRN devices. In this paper, we propose a framework for biochemical computation using systems chemistry. We present the initial components of our approach: an abstract chemical reaction dialect implemented as a multi-level intermediate representation (MLIR) compiler extension and a pathway to represent mathematical problems with CRNs. To showcase the potential of this approach, we emulate a simplified chemical reservoir device. This work lays the groundwork for leveraging chemistry's computing potential in creating energy-efficient, high-performance computing systems tailored to contemporary computational needs.

In modern computing systems, compilation employs numerous optimization techniques to enhance code performance. Source-to-source code transformations, which include control flow and datapath transformations, have been widely used in High-Level Synthesis (HLS) and compiler optimization. While researchers actively investigate methods to improve performance with source-to-source code transformations, they often overlook the significance of verifying their correctness. Current tools cannot provide a holistic verification of these transformations. This paper introduces HEC, a framework for equivalence checking that leverages the e-graph data structure to comprehensively verify functional equivalence between programs. HEC utilizes the MLIR as its frontend and integrates MLIR into the e-graph framework. Through the combination of dynamic and static e-graph rewriting, HEC facilitates the validation of comprehensive code transformations. We demonstrate effectiveness of HEC on PolyBenchC benchmarks, successfully verifying loop unrolling, tiling, and fusion transformations. HEC processes over 100,000 lines of MLIR code in 40 minutes with predictable runtime scaling. Importantly, HEC identified two critical compilation errors in mlir-opt: loop boundary check errors causing unintended executions during unrolling, and memory read-after-write violations in loop fusion that alter program semantics. These findings demonstrate HEC practical value in detecting real-world compiler bugs and highlight the importance of formal verification in optimization pipelines.

This paper presents a methodology for the Synthesis of PARallel multi-Threaded Accelerators (SPARTA) from OpenMP annotated C/C++ specifications. SPARTA extends an open-source HLS tool, enabling the generation of accelerators that provide latency tolerance for irregular memory accesses through multithreading, support fine-grained memory-level parallelism through a hot-potato deflection-based network-on-chip (NoC), support synchronization constructs, and can instantiate memory-side caches. Our approach is based on a custom runtime OpenMP library, providing flexibility and extensibility. Experimental results show high scalability when synthesizing irregular graph kernels. The accelerators generated with our approach are, on average, 2.29x faster than state-of-the-art HLS methodologies.