In Embedded and Cyber-Physical Systems (E&CPS) the functional and temporal interactions between the digital and physical parts are crucial. In these systems, most of the functionality is implemented by software deployed on heterogeneous, distributed platforms so its performance largely affects the whole E&CPS behavior. Their HW/SW co-design requires fast and accurate simulation tools capable of evaluating the performance of each platform configuration for the applications selected while minimizing software porting needs. Host-compiled simulation avoids porting, but has limitations to obtain accurate results due to the difficulty of extracting and modeling the microarchitectural details of the target platforms while maintaining simulation speed. To solve that, this work proposes replacing the traditional approach of generating code annotations with all processor internal details by the use of neural networks. Training the neural network for a specific processor enables considering its internal details when estimating the cost of executing each basic block of the software in the target processor.

Drone-based service and product innovation is curtailed by the growing dependence on poorly inter-operable proprietary technologies as well as by the risks posed to people on the ground, to other vehicles and to property (e.g. critical infrastructure). Regarding the innovation aspect, the Single European Sky Air Traffic Management (SESAR) Joint Research Undertaking is developing U-space, a set of services and procedures to help drones access airspace safely and efficiently. The aim of COMP4DRONES is to complements SESAR JU efforts by providing a framework of key enabling technologies for safe and autonomous drones with a specific focus on U2 and U3. The COMP4DRONES project has contributed to support (1) efficient customization and incremental assurance of drone-embedded platforms, (2) safe autonomous decision making concerning individual or cooperative missions, (3) trustworthy drone-to-drone and drone-to-ground communications even in presence of malicious attackers and under the intrinsic platform constraints, and (4) agile and cost-effective design and assurance of drone modules and systems. In this paper, we discuss the results of COMP4DRONES project to complement SESAR JU efforts with a particular focus on safe software and hardware drone architectures.

Design of applications for microcontrollers is typically constrained by the limited hardware capabilities of this devices. As embedded systems, the specificities of each application should be analyzed to overcome these limitations, but this is not easy to do. To help in this process, this paper proposes an analysis of some communication semantics, its potential impact on data memory usage and alternatives to minimize it. Moreover, a design tool capable of automatically generate code for microcontrollers from UML models is proposed. That way, engineers can automatically generate implementations from the communication semantics specified in the UML model. That way, exploration of the design alternatives can be done with minimal recoding effort.

Drones/UAVs are able to perform air operations that are very difficult to be performed by manned aircrafts. In addition, drones’ usage brings significant economic savings and environmental benefits, while reducing risks to human life. In this paper, we present key technologies that enable development of drone systems. The technologies are identified based on the usages of drones (driven by COMP4DRONES project use cases). These technologies are grouped into four categories: U-space capabilities, system functions, payloads, and tools. Also, we present the contributions of the COMP4DRONES project to improve existing technologies. These contributions aim to ease drones’ customization, and enable their safe operation.

New services and business models based on drones are continuously being proposed. System engineering for these services have to include simulation as the cost of detecting design mistakes during the first prototype flights may be very high. If this fact is true in any complex system, in the case of drone-based services design mistakes may compromise the drones and the payload they carry increasing the associated cost. System verification has to be made at different abstraction levels so that each design step is verified. As a consequence, a multilevel simulation framework is needed. In this paper, such a simulation framework is proposed able to verify the system functionality and performance along the design process.

Smart Robots are an integral part of the 4th Industrial Revolution. Its integration as essential components in robot-based services is not straightforward. Each robot is a cyber-physical system (CPS) where a mechanical part operates under the control of a digital board(s). Modeling and simulation of such devices has specificities to be taken into account. Model-Driven Design (MDD) has proven to be a powerful System Engineering methodology able to cope with the complexity of services built as a system of CPSs (CPSoS). In this paper, a methodology is proposed to seamlessly integrate robots into a MDD framework so that the whole service can be simulated and its performance, analyzed. Although the methodology is valid for robots in general, it has been assessed on a drone-based service.

Model-Driven Design (MDD) has proven to be a powerful technology to address the development of increasingly complex embedded systems. Beyond complexity itself, challenges come from the need to deal with parallelism and heterogeneity. System design must target different execution platforms with different OSs and HW resources, even bare-metal, support local and distributed systems, and integrate on top of these heterogeneous platforms multiple functional component coming from different sources (developed from scratch, legacy code and third-party code), with different behaviors operating under different models of computation and communication. Additionally, system optimization to improve performance, power consumption, cost, etc. requires analyzing huge lists of possible design solutions. Addressing these challenges require flexible design technologies able to support from a single-source model its architectural mapping to different computing resources, of different kind and in different platforms. Traditional MDD methods and tools typically rely on fixed elements, which makes difficult their integration under this variability. For example, it is unlikely to integrate in the same system legacy code with a third-party component. Usually some re-coding is required to enable such interconnection. This paper proposes a UML/MARTE system modeling methodology able to address the challenges mentioned above by improving flexibility and scalability. This approach is illustrated and demonstrated on a flight management system. The model is flexible enough to be adapted to different architectural solutions with a minimal effort by changing its underlying Model of Computation and Communication (MoCC). Being completely platform independent, from the same model it is possible to explore various solutions on different execution platforms.

The idea of having drones into the national airspace raises serious concerns. These concerns are for nearly all spectrum of society which ranges from government facilities and aviation authorities to private citizens. To guarantee a high level of safety and security, drones must be implemented as highly constrained systems with a certain number of functions (technologies). In this paper, we identify the key technologies for drones based on their common and specific usages. These technologies are grouped into four categories: U-space capabilities, system functions, payloads, and tools. We also list the contributions of COMP4DRONES project in terms of improving technologies and easing drone customization including its safe operations.

The purpose of this paper is to introduce run time monitoring infrastructures and to analyze trace data inside a well-established component-based methodology. The goal is to show the concept among different monitoring requirements by defining a general reference architecture that can be adapted to different scenarios. Starting from design artifacts, generated by a system engineering modeling tool, and source code automatically generated from UML models, a custom Hardware monitoring sub-system infrastructure will be presented. This sub-system will be able to generate run-time artifacts for run-time verification. We will show how the framework provides round-trip support in the development chain, injecting monitoring requirements from design models down to code and its execution on the platform and trace data back to the models, where the expected behavior will then be compared with the actual behavior. This approach will be used towards optimizing design models for specific properties (e.g, for system performance), using a specific constraint approach compliant with UML standards. Industrial and custom use cases will be used to demonstrate the effectiveness of this approach in real scenarios.

The design of increasingly complex embedded systems requires powerful solutions from the very beginning of the design process. Model Based Design (MBD) and early simulation have proven to be capable technologies to perform initial design space analysis to optimize system design. Traditional MBD methods and tools typically rely on fixed elements, which makes difficult the evaluation of different platform configurations, communication alternatives or models of computation. Addressing these challenges require flexible design technologies able to support, from a high-level abstract model, full design space exploration, including system specification, binary generation and performance evaluation. In this context, this paper proposes a UML/MARTE based approach able to address the challenges mentioned above by improving design flexibility and evaluation capabilities, including automatic code generation, trace execution collection and trace analysis from the initial UML models. The approach focuses on the definition and analysis of the paths data follow through the different application components, as a way to understand the behavior or the different design solutions.

Space applications rely on long and complex design processes, as they must deal with strict non-functional requirements such as criticality, timeliness, reliability and safety. The huge number of analysis and evaluations performed requires powerful simulations technologies combining high simulation speed and accuracy. Host-compiled simulation is a powerful approach to achieve fast, timed simulation of software running in complex embedded systems. However, in the general term, there is still the need of improving the speed and accuracy of these solutions, and there is a lack of host-compiled approaches oriented to space applications. To solve the first point, this paper presents an alternative that modifies the standard solution of adding the modeling of the cross-compiled control flow in the host computer by modifying the compiler's intermediate representation. That way, the host binary naturally follows the cross-compiled binary flow, avoiding a separate modeling, and improving simulation speed while maintaining accuracy. Additionally, the paper focuses on LEON processor, commonly used by the European Space Agency (ESA).

This paper introduces the concept of Semi-static Operator Graphs (SOG) to provide a runtime reconfigurable accelerator for query execution based on a Field Programmable Gate Array (FPGA). Instead of generating an FPGA configuration for a given arbitrary query during system runtime, we deploy a general query structure on the FPGA consisting of multiple small reconfigurable partitions (RP). During deployment of the hybrid database system, for each RP various query operators are prepared as reconfigurable modules (RM). At system runtime, the proposed approach dynamically chooses and reconfigures RMs into the RPs regarding a given query. As a result the reconfiguration overhead during system runtime is significantly reduced and enables the utilization of our hybrid architecture in real-world scenarios.

Efficient design of complex multiprocessor embedded systems requires fast technologies for early system cosimulation and evaluation. Host-compiled simulation has been proposed as an option for this purpose, since it enables accurately timed modeling at high simulation speeds. To achieve high accuracy, simulation technology has to consider internal details of the processing system, such as the modeling of processor pipelines or theestimation of cache misses. However, the modeling of these details must involve low overhead to ensure simulation speed. This paper proposes adding the modeling of the impact of a write buffer in write-through policies. The scheme presented is oriented to maximizing the accuracy vs. speed balance, proposing a static solution that results in no additional simulation overhead.

This work receives funding from the Spanish Government under grant number TIN2014-56158-C4-2-P (M2C2), and from the Electronic Component Systems for European Leadership Joint Undertaking under grant agreement No 737494 (MegaM@RT2). This Joint Undertaking receives support from the European Union’s Horizon 2020 research and innovation programme and Sweden, France, Spain, Italy, Finland, Czech Republic. We thank the anonymous reviewers for their insights and proposals of improvements

During the last years, the market of embedded vision-based systems has been growing at an accelerated rate. Virtual and augmented reality has the potential to become one of the most innovative technologies for the next decade. One of the most important aspects of these technologies is related to the spatial location of objects or people in defined environments, for which there are several techniques. One of the most widely used is based on visual marker recognition. The main problems of these approaches are related to the accuracy, the changing environments, the processing time, the operating range/distance and the price. The popularization of these technologies produces a pull effect toward the companies developing the best technology at the lowest price. This paper proposes a marker design and an algorithm to detect the markers under different ambient conditions, with a long range to be executed on embedded systems with low computational requirements. The proposed method reduces the existing problems in the state-of-the-art related to the use of different environments and conditions such as different distances or different illumination. Moreover, the requisites of the method are minimal to reduce the cost of deployment.

Model-based design has shown to be a powerful approach for embedded software systems. The Unified Modeling Language (UML) provides a standard, graphically based formalism for capturing system models. The standard Modeling and Analysis of Real-Time Embedded Systems (MARTE) profile provides syntactical and semantical extensions required for the modeling and HW/SW codesign of real-time and embedded systems. However, the UML/MARTE standard is not sufficient. In addition, a modeling methodology stating how to build a model capable to support the analysis and HW/SW codesign activities of complex embedded systems is required. This chapter presents a UML/MARTE modeling methodology capable to address such analysis and design activities. A distinguishing aspect of the modeling methodology is that it supports a single-source design approach.

In order to prepare the students for their future professional performance, it is necessary to propose complex and realistic practical activities. However, in order to be carried out, this kind of activities typically requires a considerable amount of time, resources, and collateral knowledge. To overcome these difficulties, this paper presents a subject in a Telecommunication Engineering Degree, taught making use of different professional materials. By using these materials, it is easier to transmit information to the students through case-study methodologies. In addition, their use simplifies the preparation of problems and complex projects without generating the perception that the problems proposed are mostly resolved thanks to teaching help instead of student's performance. To demonstrate these ideas, this paper focuses on three experiences covered by the subject: one based on the use of Web resources, one using information from a professional design contest, and the last one focused on technical datasheets and application notes. These experiences have been selected in order to achieve an adequate degree of difficulty and to be attractive for students.

The increasing processing power of today's HW/SW platforms leads to the integration of more and more functions in a single device. Additional design challenges arise when these functions share computing resources and belong to different criticality levels. The paper presents the CONTREX European project and its preliminary results. CONTREX complements current activities in the area of predictable computing platforms and segregation mechanisms with techniques to consider the extra-functional properties, i.e., timing constraints, power, and temperature. CONTREX enables energy efficient and cost aware design through analysis and optimization of these properties with regard to application demands at different criticality levels.